PCAL6408AHKX NXP Semiconductors, PCAL6408AHKX Datasheet - Page 11

• Manufacturer Part Number: PCAL6408AHKX
• Description: Interface - I/O Expanders 8bit I2C/SMBus IO Expander w/Interrupt
• Manufacturer: NXP Semiconductors

Specifications of PCAL6408AHKX

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: XQFN-16
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders

NXP Semiconductors
PCAL6408A
Product data sheet
7.4.7 Pull-up/pull-down enable register (43h)
7.4.8 Pull-up/pull-down selection register (44h)
7.4.9 Interrupt mask register (45h)
Table 13.
This register allows the user to enable or disable pull-up/pull-down resistors on the I/O
pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting
the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the
resistors will be disconnected when the outputs are configured as open-drain outputs (see
Section
pull-down resistor.
Table 14.
The I/O port can be configured to have pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
Table 15.
Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system
start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an
input changes state and the corresponding bit in the Interrupt mask register is set to 1, the
interrupt is masked and the interrupt pin (INT) will not be asserted. If the corresponding bit
in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.
If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1,
the interrupt pin will be de-asserted.
Table 16.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
7.4.11). Use the pull-up/pull-down selection registers to select either a pull-up or
Input latch register (address 42h)
Pull-up/pull-down enable register (address 43h)
Pull-up/pull-down selection register (address 44h)
Interrupt mask register (address 45h)
PUD7
PE7
M7
L7
7
0
7
0
7
1
7
1
All information provided in this document is subject to legal disclaimers.
PUD6
Rev. 2 — 6 December 2012
PE6
M6
L6
6
0
6
0
6
1
6
1
Low-voltage translating, 8-bit I
PUD5
PE5
M5
L5
5
0
5
0
5
1
5
1
PUD4
PE4
M4
L4
4
0
4
0
4
1
4
1
PUD3
PE3
M3
L3
3
0
3
0
3
1
3
1
2
C-bus/SMBus I/O expander
PUD2
PE2
M2
L2
PCAL6408A
2
0
2
0
2
1
2
1
© NXP B.V. 2012. All rights reserved.
PUD1
PE1
M1
L1
1
0
1
0
1
1
1
1
PUD0
PE0
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M0
L0
0
0
0
0
0
1
0
1