MAX11014BGTM+ Maxim Integrated, MAX11014BGTM+ Datasheet - Page 43

• Manufacturer Part Number: MAX11014BGTM+
• Description: Special Purpose Amplifiers Auto RF MESFET Amp Drain-Current Cntrlr
• Manufacturer: Maxim Integrated
• Series: MAX11014, MAX11015r

Specifications of MAX11014BGTM+

• Rohs: yes
• Common Mode Rejection Ratio (min): 90 dB
• Operating Supply Voltage: 0.5 V to 11 V
• Supply Current: 2.8 mA
• Maximum Power Dissipation: 2162.2 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-48
• Available Set Gain: 13.98 dB

Set the VALARM1 bit, D5, to 1 to enable ALARM func-
tionality for GATE1 voltage measurements. Set the
VWIN1 bit, D4, to 1 to monitor the GATE1 voltage with
the ALARM comparator in windowing mode. Set VWIN1
to 0 to monitor the GATE1 voltage with the ALARM com-
parator in hysteresis mode. Set the TALARM1 bit, D3, to
1 to enable ALARM functionality for channel 1 tempera-
ture measurements. Set the TWIN1 bit, D2, to 1 to moni-
tor the channel 1 temperature with the ALARM
comparator in windowing mode. Set TWIN1 to 0 to moni-
tor the channel 1 temperature with the ALARM compara-
tor in hysteresis mode. Set the IALARM1 bit, D1, to 1 to
enable ALARM functionality for channel 1 sense voltage
(RCS1+ to RCS1-) measurements. Set the IWIN1 bit, D0,
to 1 to monitor the channel 1 sense voltage with the
ALARM comparator in windowing mode. Set IWIN1 to 0
to monitor the channel 1 sense voltage with the ALARM
comparator in hysteresis mode.
Write to the channel 1/channel 2 V
the V
Writing to these registers triggers a V
lation. That code is then loaded into either the channel
1/channel 2 DAC input register or channel 1/channel 2
DAC input and output register, depending on the state
of the LDAC1/LDAC2 bits in the software configuration
register. Set the command byte to 40h to write to the
channel 1 V
to write to the channel 2 V
Bits D15–D12 are don’t care. Bits D11–D0 contain the
straight binary data.
Table 14. VSET1 and VSET2 (Write)
Table 15. USRK1 and USRK2 (Write)
VSET11–VSET0
BIT NAME
BIT NAME
K11–K0
SET(CODE)
X
X
SET
register. Set the command byte to 42h
code in the V
______________________________________________________________________________________
DATA BIT
DATA BIT
D15–D12
D15–D12
D11–D0
D11–D0
SET
VSET1 and VSET2 (Write)
register. See Table 14.
DAC(CODE)
0000 0000 0000
RESET STATE
RESET STATE
SET
DAC(CODE)
Automatic RF MESFET Amplifier
registers to set
N/A
X
X
equations.
calcu-
Don’t care.
VSET11 is the MSB and VSET0 is the LSB. Data format is straight binary.
Don’t care.
K11 is the MSB and K0 is the LSB. Data format is straight binary.
Drain-Current Controllers
Write to the channel 1/channel 2 K parameter registers
to set the LUT
The K parameter register value is loaded into the
V
KSRC_-0 bits in the software configuration register are
set to 010, 101, 110, or 111. See Table 11b. Use the K
parameter as an index to the KLUT or as a multiplier for
the V
writing to the software configuration register. See Table
11. Set the command byte to 44h to write to the channel
1 K parameter register. Set the command byte to 46h to
write to the channel 2 K parameter register. See Table
15. Bits D15–D12 are don’t care. Bits D11–D0 contain
the straight binary data.
Write to the channel 1/channel 2 DAC input registers to
load the DAC code and bypass a V
tion. Transfer the code written to the DAC input registers
to the channel 1/channel 2 DAC output registers by set-
ting the corresponding DACCH_ bit high in the software
load DAC register. Set the command byte to 48h and
4Ch, respectively, to write to the channel 1/channel 2
DAC input registers. See Table 16. Bits D15–D12 are
don’t care. Bits D11–D0 contain the straight binary data.
Writing to these registers overwrites any previous val-
ues loaded from the V
DAC(CODE)
DAC(CODE)
equation when the KSRC_-2/KSRC_-1/
K
[K] code in the V
equation in place of V
FUNCTION
FUNCTION
DAC(CODE)
IPDAC1 and IPDAC2 (Write)
USRK1 and USRK2 (Write)
calculation.
DAC(CODE)
DAC(CODE)
SET(CODE)
equation.
calcula-
by
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