MAX11014BGTM+ Maxim Integrated, MAX11014BGTM+ Datasheet - Page 50

• Manufacturer Part Number: MAX11014BGTM+
• Description: Special Purpose Amplifiers Auto RF MESFET Amp Drain-Current Cntrlr
• Manufacturer: Maxim Integrated
• Series: MAX11014, MAX11015r

Specifications of MAX11014BGTM+

• Rohs: yes
• Common Mode Rejection Ratio (min): 90 dB
• Operating Supply Voltage: 0.5 V to 11 V
• Supply Current: 2.8 mA
• Maximum Power Dissipation: 2162.2 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-48
• Available Set Gain: 13.98 dB

Read the oldest result in the FIFO by writing command
byte 80h and reading the next 16 bits at DOUT in SPI
mode and SDA in I
tag) identify which ADC or LUT channel is being con-
verted. Bits D11–D0 contain the ADC/LUT conversion
results for that specific channel. Bit D11 is the MSB and
bit D0 is the LSB for all ADC and LUT data, with the
exception of the LUT configuration words. When read-
ing the LUT configuration registers, bit D12 is the MSB
and bit D0 is the LSB. See Table 25.
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 26. FLAG (Read)
50
BIT NAME
ADCBUSY
ALUBUSY
PGABUSY
RESTART
FIFOEMP
FIFOOVR
VGBUSY
______________________________________________________________________________________
X
DATA BIT
D15–D7
2
D6
D5
D4
D3
D2
D1
D0
C mode. Bits D15–D12 (channel
RESET
X
0
0
0
0
1
1
0
Don’t care.
RESTART is set to 1 after either a watchdog timer reset or by commanding a
software reset through the software clear register’s FULL RESET function.
RESTART returns to 0 after a power-on reset or a flag register read command.
ALUBUSY is set to 1 when the ALU is performing other tasks not covered by
specific status bits elsewhere in this register. This includes, for example, the
internal memory initialization after power-up.
PGABUSY is set to 1 when the ALU is performing a PGA calibration (whether
commanded or self-timed).
ADCBUSY is set to 1 when the ADC is busy, an ALARM value is being checked,
or the ADC results are being loaded into the FIFO. ADCBUSY returns to 0 after
the ADC completes all of the conversions in the current scan.
VGBUSY is set to 1 when the ALU is performing a lookup and interpolation or
V
FIFOEMP is set to 1 when the FIFO is empty and contains no data. FIFOEMP is
reset to 0 if data is written into the FIFO. Writing to the software clear register with
FIFOCLR set to 1 causes the FIFO to be cleared, which then sets FIFOEMP to 1.
FIFOOVR functions in one of two modes:
1) Reading the ADC data: FIFOOVR is set to 1 if the FIFO has a data overflow.
FIFOOVR is reset to 0 by reading the flag register or by clearing the FIFO
through the software clear register. Emptying the FIFO does not clear the
FIFOOVR bit.
2) Reading the LUT data: When commanding an LUT read, the FIFO is no longer
allowed to overflow (as it is for normal ADC monitoring). FIFOOVR is set to 1 if
the LUT is full and set to 0 if the LUT is not full, for that instant in time only.
DAC(CODE)
FIFO
calculation for either channel.
Read from the flag register to determine the source of a
busy condition. Set the command byte to F6h to read
the flag register. Bits D15–D7 are don’t care. See Table
26. The RESTART bit, D6, is set to 1 after either a
watchdog timer reset or by commanding a software
reset through the software clear register’s FULL RESET
function. RESTART is reset to a 0 after a power-on reset
or a flag register read command. The ALUBUSY bit,
D5, is set to 1 when the ALU is performing other tasks
not covered by specific status bits elsewhere in this
register. The PGABUSY bit, D4, is set to 1 when the
ALU is performing a PGA calibration.
FUNCTION
FLAG (Read)