74ABT16501CMTDX Fairchild Semiconductor, 74ABT16501CMTDX Datasheet

74ABT16501CMTDX

Manufacturer Part Number

74ABT16501CMTDX

Description

IC UNIV BUS TXRX 18BIT 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ABTr

Datasheet

1.74ABT16501CMTDX.pdf (7 pages)

Specifications of 74ABT16501CMTDX

Logic Type

Universal Bus Transceiver

Number Of Circuits

18-Bit

Current - Output High, Low

3mA, 64mA

Voltage - Supply

4.5 V ~ 5.5 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ABT16501CSSC

74ABT16501CMTD

74ABT16501

18-Bit Universal Bus Transceivers with 3-STATE Outputs

General Description

The ABT16501 18-bit universal bus transceiver combines

D-type latches and D-type flip-flops to allow data flow in

transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is

HIGH. When LEAB is LOW, the A data is latched if CLKAB

is held at a HIGH or LOW logic level. If LEAB is LOW, the A

bus data is stored in the latch/flip-flop on the LOW-to-HIGH

transition of CLKAB. Output-enable OEAB is active-high.

When OEAB is HIGH, the outputs are active. When OEAB

is LOW, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

Ordering Code:

Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Pin Assignment for SSOP

Package Number

MS56A

MTD56

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS011690.prf

plementary (OEAB is active HIGH and OEBA is active

LOW).

To ensure the high-impedance state during power up or

power down, OE inputs should be tied to GND through a

pulldown resistor; the minimum value of the resistor is

determined by the current-sourcing capability of the driver.

Features

Function Table

Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 2: Output level before the indicated steady-state input conditions

were established.

Note 3: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was HIGH before LEAB went LOW.

Combines D-Type latches and D-Type flip-flops for oper-

ation in transparent, latched, or clocked mode

Flow-through architecture optimizes PCB layout

Guaranteed latch-up protection

High impedance glitch free bus loading during entire

power up and power down cycle

Non-destructive hot insertion capability

OEAB

Package Description

LEAB

Inputs

CLKAB

(Note 1)

January 1995

Revised January 1999

www.fairchildsemi.com

Output

(Note 2)

(Note 3)

Related parts for 74ABT16501CMTDX

74ABT16501CMTDX Summary of contents

Page 1

... Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for SSOP © 1999 Fairchild Semiconductor Corporation plementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE inputs should be tied to GND through a pulldown resistor ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 5) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...

Page 4

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW ...

Page 5

Capacitance Symbol Parameter C Input Capacitance IN C (Note 10) Output Capacitance I/O Note 10 measured at frequency f 1 MHz per MIL-STD-883, Method 3012. I/O AC Loading *Includes jig and probe capacitance. FIGURE 1. Standard AC Test ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE ...

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