74VHC164N_Q Fairchild Semiconductor, 74VHC164N_Q Datasheet - Page 2
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74VHC164N_Q
Manufacturer Part Number
74VHC164N_Q
Description
Counter Shift Registers 8-Bit Shift Register
Manufacturer
Fairchild Semiconductor
Datasheet
1.74VHC164MTC_Q.pdf
(10 pages)
Specifications of 74VHC164N_Q
Counting Sequence
Serial to Parallel
Number Of Circuits
8
Package / Case
PDIP-14
Logic Family
74VHC
Logic Type
CMOS
Number Of Input Lines
2
Output Type
Serial / Parallel
Propagation Delay Time
16.3 ns, 11 ns
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Function
Shift Register
Mounting Style
Through Hole
Number Of Output Lines
8
Operating Supply Voltage
2 V to 5.5 V
Supply Voltage - Max
5.5 V
©1993 Fairchild Semiconductor Corporation
74VHC164 Rev. 1.4.0
Connection Diagram
Pin Description
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
logical AND of the two data inputs (A • B) that existed
before the rising clock edge. A LOW level on the Master
Reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all Q outputs LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
A, B
CP
MR
Q
Names
0
–Q
Pin
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Description
0
the
2
Logic Symbol
Function Table
H
L
X
Q
referenced input or output one setup time prior to
the LOW-to-HIGH clock transition.
Reset (Clear)
Shift
Operating
LOW Voltage Levels
Immaterial
HIGH Voltage Levels
Lower case letters indicate the state of the
Mode
MR
H
H
H
H
L
Inputs
A
H
H
X
L
L
B
X
H
H
L
L
Q
H
L
L
L
L
0
Outputs
www.fairchildsemi.com
Q
Q
Q
Q
Q
L–L
1
0
0
0
0
–Q
–Q
–Q
–Q
–Q
6
6
6
6
7