74ALVC162601T Fairchild Semiconductor, 74ALVC162601T Datasheet

74ALVC162601T

Manufacturer Part Number

74ALVC162601T

Description

TXRX 18BIT UNIV BUS LV 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC162601T.pdf (7 pages)

Specifications of 74ALVC162601T

Logic Type

Universal Bus Transceiver

Number Of Circuits

18-Bit

Current - Output High, Low

24mA, 24mA; 12mA, 12mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC162601T

74ALVC162601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

and 26 Ω Series Resistors in the B-Port Outputs

General Description

The 74ALVC162601, 18-bit universal bus transceiver, com-

bines D-type latches and D-type flip-flops to allow data flow

in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the HIGH-impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The 74ALVC162601 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC162601 is also designed with 26 Ω series

resistors in the B-Port outputs. This design reduces line

noise in applications such as memory address drivers,

clock drivers, and bus transceivers/transmitters.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O compatibility up to 3.6V.

Package

Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500676

Features

I 1.65V–3.6V V

I 3.6V tolerant inputs and outputs

I 26 Ω series resistors in B-Port outputs

I t

I Power-down high impedance inputs and outputs

I Supports live insertion/withdrawal (Note 1)

I Uses patented noise/EMI reduction circuitry

I Latchup conforms to JEDEC JED78

I ESD performance:

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

4.3 ns max for 3.0V to 3.6V V

5.1 ns max for 2.3V to 2.7V V

9.2 ns max for 1.65V to 1.95V V

Human body model > 2000V

Machine model > 200V

(A to B)

Package Description

supply operation

through a pull-up resistor; the minimum

September 2001

Revised October 2001

www.fairchildsemi.com

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74ALVC162601T Summary of contents

Page 1

... Ordering Code: Package Order Number Number 74ALVC162601T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features I 1.65V– ...

Page 2

Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A –A Side A Inputs 3-STATE Outputs B –B Side B ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( − 0. Output Voltage (V ) (Note Input Diode Current ( < Output Diode Current ...

Page 4

DC Electrical Characteristics Symbol Parameter I High Level Output Current OH A Outputs High Level Output Current B Outputs I Low Level Output Current OL A Outputs Low Level Output Current B Outputs I Input Leakage Current I I 3-STATE ...

Page 5

AC Electrical Characteristics Symbol Parameter Output Disable Time PLZ PHZ OEBA to A Output Disable Time OEAB to B Symbol Parameter V t Setup Time S t Hold Time H t Pulse Width W Capacitance Symbol ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit ( Input Charactertistics 1MHz; t Symbol 3.3V ± 0. − 0. ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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