GTLP16T1655MTD Fairchild Semiconductor, GTLP16T1655MTD Datasheet

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GTLP16T1655MTD

Manufacturer Part Number
GTLP16T1655MTD
Description
IC UNIV BUS TXRX 16BIT 64TSSOP
Manufacturer
Fairchild Semiconductor
Series
74GTLPr
Datasheet

Specifications of GTLP16T1655MTD

Logic Type
Universal Bus Transceiver
Number Of Circuits
16-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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© 2005 Fairchild Semiconductor Corporation
GTLP16T1655MTD
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
with High Drive GTLP and Individual Byte Controls
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing ( 1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
MTD64
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500172
Features
Bidirectional interface between GTLP and LVTTL logic
levels
Variable edge rate control pin to select desired edge rate
on the GTLP backplane (V
V
receiver threshold adjustibility
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
TTL compatible driver and control inputs
Designed using Fairchild advanced BiCMOS technology
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
Power up/down and power off high impedance for live
insertion
Open drain on GTLP to support wired-or connection
Flow through pinout optimizes PCB layout
D-type flip-flop, latch and transparent data paths
A Port source/sink 24mA/ 24mA
B Port sink 100mA
Partitioned as two 8-bit transceivers with individual latch
timing and output control but with a common clock
External pin to pre-condition I/O capacitance to high
state (V
REF
Package Description
pin provides external supply reference voltage for
CCBIAS
)
ERC
August 1998
Revised January 2005
)
www.fairchildsemi.com

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GTLP16T1655MTD Summary of contents

Page 1

... Ordering Code: Order Number Package Number GTLP16T1655MTD MTD64 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation ...

Page 2

Connection Diagram Truth Tables (Note 1) Inputs OEAB LEAB Inputs OE OEAB OEBA (Note 4) (Note ...

Page 3

Functional Description The GTLP16T1655 is a high drive (100 mA) 16-bit univer- sal bus transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. The device is uniquely partitioned as two 8-bit transceivers with individual latch ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 6) DC Output Sink Current into A Port Output Source Current from ...

Page 5

DC Electrical Characteristics Symbol I A Port V 3.6V OZH CC B Port I A Port V 3.6V OZL CC B Port I A Port 1.5V OZPU CC (Note 10 ...

Page 6

Electrical Characteristics (GTLP) Over recommended range of supply voltage and operating free-air temperature, V otherwise noted for B Port and C L From Parameter (Input) f MAX t B PLH t PHL t ...

Page 7

Electrical Characteristics (GTLP) Over recommended range of supply voltage and operating free air temperature for B Port and for A Port From Symbol (Input) f MAX t ...

Page 8

Extended Electrical Characteristics (GTLP) Over recommended ranges of supply voltage and operating free-air temperature for B Port and for A Port Symbol t (Note 15) OSLH t (Note 15) OSHL t ...

Page 9

AC Operating Requirements (GTL) Over recommended ranges of supply voltage and operating free-air temperature, V Parameter f Maximum Clock Frequency MAX t Pulse Duration WIDTH t Setup Time SU t Hold Time HOLD Electrical Characteristics (GTL) ...

Page 10

Electrical Characteristics (GTL) Over recommended range of supply voltage and operating free air temperature for B Port and for A Port From Symbol (Input) f MAX t ...

Page 11

Extended Electrical Characteristics (GTL) Over recommended ranges of supply voltage and operating free-air temperature for B Port and for A Port Symbol (Input) t (Note 21) OSLH t (Note 21) OSHL ...

Page 12

Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Voltage Waveform - Propagation Delay Times Voltage Waveform - Pulse Width All input ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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