GTLP18T612MTDX Fairchild Semiconductor, GTLP18T612MTDX Datasheet
GTLP18T612MTDX
Specifications of GTLP18T612MTDX
Related parts for GTLP18T612MTDX
GTLP18T612MTDX Summary of contents
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... The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gun- ning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated ...
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Connection Diagrams Pin Assignments for SSOP and TSSOP Pin Assignments for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB A-to-B Output Enable (Active LOW) (LVTTL Level) OEBA B-to-A Output Enable (Active LOW) (LVTTL Level) CEAB A-to-B Clock/LE ...
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Functional Description The GTLP18T612 bit registered transceiver con- taining D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 7) 0. Output Sink Current into A Port Output ...
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DC Electrical Characteristics Symbol I A Port and V 3.45V (Note 12) Control Pins A or Control Inputs Control Pins i A Port B Port Note 9: All typical values are at V 3.3V, V ...
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AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature for B Port and for A Port From Symbol (Input PLH t PHL t LEAB PLH ...
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Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Note A: C includes probes and Jig capacitance. L Voltage Waveform - Propagation ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 9 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...