NAND04GW3B2DN6E NUMONYX, NAND04GW3B2DN6E Datasheet - Page 30

• Manufacturer Part Number: NAND04GW3B2DN6E
• Description: IC FLASH 4GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND04GW3B2DN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device operations
Table 11.
Figure 14. Copy back program (without readout of data)
1. Copy back program is only permitted between odd address pages or even address pages.
30/72
RB
I/O
Read
Code
00h
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC (error detection
code) during a copy back operation. Consequently, it is no longer required to use an external
ECC to detect copy back operation errors. Read error occurrences can be detected by
checking the EDC status register (see
Section 6.9
The copy back program operation requires the following four steps:
1.
2.
3.
To see the data input cycle for modifying the source page and an example of the copy back
program operation, refer to
Figure 16: Page copy back program with random data input
modify a portion or a multiple distant portion of the source page.
Copy back program addresses
The first step reads the source page. The operation copies all 2112 bytes from the
page into the data buffer. It requires:
–
–
–
When the device returns to the ready state (ready/busy High), optional data readout is
allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus
cycles to input the target page address. See
the same for the source and target page.
Issue the confirm command to start the P/E/R controller.
Add Inputs
Source
Density
1 bus write cycle to set up the command
5 bus write cycles to input the source page address
1 bus write cycle to issue the confirm command code
4 Gbits
8 Gbits
for details of EDC operations.
(Read Busy time)
tBLBH1
35h
Busy
Figure 14: Copy back program (without readout of
Copy Back
Code
85h
Section 6.13: Read EDC status
Add Inputs
Target
Source and target page addresses
Table 11
(Program Busy time)
Same A18 and A30
NAND04G-B2D, NAND08G-BxC
for the addresses that must be
shows a data input cycle to
Same A18
tBLBH2
10h
Busy
Read Status Register
register). See also
70h
data).
SR0
ai09858b