NAND04GW3B2DN6E NUMONYX, NAND04GW3B2DN6E Datasheet - Page 54

• Manufacturer Part Number: NAND04GW3B2DN6E
• Description: IC FLASH 4GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND04GW3B2DN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC and AC parameters
Table 31.
1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See
2. ES = electronic signature.
3.
4. During a program/erase enable operation, t
54/72
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
ALLRL1
ALLRL2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EHALX
EHCLX
t
WHWH
BLBH1
BLBH2
BLBH3
BLBH4
CLLRL
WHBH
WHRL
RHWL
VHWH
EHQZ
RHQZ
EHQX
RHQX
WHBL
VLWH
BHRL
ELQV
RHRL
RLQX
RLRH
RLQV
DZRL
RLRL
Figure
During a program/erase disable operation, t
t
ADL
is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
42.
t
t
t
t
t
t
ADL
t
WW
PROG
t
RHOH
BERS
t
t
t
t
t
RLOH
t
t
t
t
Alt.
t
WHR
t
COH
t
t
RST
CLR
CHZ
CSD
RHZ
CEA
REH
t
REA
RHW
t
WB
RR
RC
t
AR
RP
IR
R
AC characteristics for operations
(3)
(4)
Address Latch Low to Read
Enable Low
Ready/Busy High to Read Enable Low
Ready/Busy Low to
Ready/Busy High
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable High to Address Latch ‘don’t care’
Chip Enable High to Command Latch ‘don’t care’
Chip Enable Low to Output Valid
Read Enable High to Read
Enable Low
Chip Enable high to Output Hold
Read Enable High to Output Hold
Read Enable Low to Output Hold (EDO mode)
Read Enable Low to Read
Enable High
Read Enable Low to Read
Enable Low
Read Enable Low to Output
Valid
Write Enable High to
Ready/Busy High
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Read Enable High to Write Enable Low
Last address latched to data loading time during program operations Min
Write protection time
Read Enable High to Output Hi-Z
WW
WW
is the delay from WP high to W High.
is the delay from WP Low to W High.
Read electronic signature
Read cycle
Read Busy time
Program Busy time
Erase Busy time
Reset Busy time, during ready
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
Read Enable High Hold time
Read Enable pulse width
Read cycle time
Read Enable access time
Read ES access time
Read Busy time
Parameter
(1)
(2)
NAND04G-B2D, NAND08G-BxC
Figure
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
40,
Figure 41
1.8 V
700
500
100
100
100
100
100
10
20
25
10
10
30
10
45
15
15
15
25
45
30
25
60
10
2
5
5
0
5
700
500
100
100
100
100
3 V
10
10
20
25
10
10
30
10
25
10
15
15
12
25
20
25
60
70
and
2
5
5
0
5
Unit
ms
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns