ATMEGA16U2-16AU Atmel, ATMEGA16U2-16AU Datasheet - Page 206

• Manufacturer Part Number: ATMEGA16U2-16AU
• Description: 8-bit Microcontrollers - MCU 16K Flash
• Manufacturer: Atmel

Specifications of ATMEGA16U2-16AU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit
• Program Memory Size: 16 KB
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Program Memory Type: Flash
• Factory Pack Quantity: 1250

21.14.2
21.14.2.1
7799D–AVR–11/10
Detailed description
Abort
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the bank is full.
The data are written by the CPU, following the next flow:
If the endpoint uses 2 banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
An “abort” stage can be produced by the host in some situations:
• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
• The CPU acknowledges the interrupt by clearing TXINI,
• The CPU can write the data into the current bank (write in UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
• after “N” write into UEDATX
• as soon as RWAL is cleared by hardware.
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice,
ATmega8U2/16U2/32U2
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