CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet

CY7C1512AV18-200BZXC

Manufacturer Part Number

CY7C1512AV18-200BZXC

Description

IC SRAM 72MBIT 200MHZ 165TFBGA

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1514AV18-167BZXC.pdf (28 pages)

2.CY7C1512AV18-200BZXC.pdf (26 pages)

3.CY7C1512AV18-200BZXC.pdf (24 pages)

4.CY7C1514AV18-200BZXI.pdf (28 pages)

Specifications of CY7C1512AV18-200BZXC

Format - Memory

RAM

Memory Type

SRAM - Synchronous, QDR II

Memory Size

72M (4M x 18)

Speed

200MHz

Interface

Parallel

Voltage - Supply

1.7 V ~ 1.9 V

Operating Temperature

0°C ~ 70°C

Package / Case

165-TFBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1512AV18-200BZXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY7C1512AV18-200BZXC

Manufacturer:

CYPRESS/赛普拉斯

Quantity:

20 000

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Download datasheet (418Kb)

Cypress Semiconductor Corporation

Document #: 38-05565 Rev. *E

Features

Configurations

CY7C1517V18 – 8M x 8

CY7C1528V18 – 8M x 9

CY7C1519V18 – 4M x 18

CY7C1521V18 – 2M x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

• 300-MHz clock for high bandwidth

• 4-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

• Two input clocks (K and K) for precise DDR timing

• Two input clocks for output data (C and C) to minimize

• Echo clocks (CQ and CQ) simplify data capture in

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

(data transferred at 600 MHz) @ 300 MHz

— SRAM uses rising edges only

clock-skew and flight-time mismatches

high-speed systems

300 MHz

300

950

•

)

198 Champion Court

72-Mbit DDR-II SRAM 4-Word Burst

278 MHz

278

900

Functional Description

The CY7C1517V18, CY7C1528V18, CY7C1519V18 and

CY7C1521V18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II (Double Data Rate) architecture. The

DDR-II consists of an SRAM core with advanced synchronous

peripheral circuitry and a two-bit burst counter. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with four 8-bit

words in the case of CY7C1517V18 and four 9-bit words in the

case of CY7C1528V18 that burst sequentially into or out of the

device. The burst counter always starts with “00” internally in

the case of CY7C1517V18 and CY7C1528V18. On

CY7C1519V18 and CY7C1521V18, the burst counter takes in

the last two significant bits of the external address and bursts

four 18-bit words in the case of CY7C1519V18, and four 36-bit

words in the case of CY7C1521V18, sequentially into or out of

the device.

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SRAM

in the system design.Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

All Synchronous Input Pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks . Writes are conducted with on-chip

synchronous self-timed write circuitry.

250 MHz

•

250

850

San Jose

200 MHz

CA 95134-1709

200

750

Revised September 25, 2006

167 MHz

CY7C1517V18

CY7C1528V18

CY7C1519V18

CY7C1521V18

Architecture

167

700

•

408-943-2600

MHz

Unit

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