CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05565 Rev. *E
Pin Definitions
DQ
LD
NWS
BWS
BWS
A, A0, A1
R/W
C
C
K
K
Pin Name
[x:0]
0
0
2
, BWS
, BWS
, NWS
1
3
1
,
Input/Output-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
I/O
Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When Read access is deselected, Q
CY7C1517V18 - DQ
CY7C1528V18 - DQ
CY7C1519V18 - DQ
CY7C1521V18 - DQ
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst of 4
data (two clock periods of bus activity).
Nibble Write Select 0, 1 − active LOW (CY7C1517V18 only). Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1528V18 − BWS
CY7C1519V18− BWS
CY7C1521V18− BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 8M x 8 (four arrays each of 2M x 8) for CY7C1517V18,
8M x 9 (four arrays each of 2M x 9) for CY7C1528V18, a single 4M x 18 array for CY7C1519V18,
and a single 2M x 36 array for CY7C1521V18.
CY7C1517V18 – Since the least two significant bits of the address internally are “00,” only 21
address inputs are needed to access the entire memory array.
CY7C1528V18 – Since the least two significant bits of the address internally are “00,” only 21
address inputs are needed to access the entire memory array.
CY7C1519V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 22 address inputs are needed to access the entire memory array.
CY7C1521V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 21 address inputs are needed to access the entire memory array.
All the address inputs are ignored when write access is deselected.
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
0
controls D
[35:27]
.
[3:0]
[7:0]
[8:0]
[17:0]
[35:0]
and NWS
0
0
0
controls D
controls D
controls D
1
controls D
[8:0]
[8:0]
[8:0]
, BWS
and BWS
[x:0]
[x:0]
Pin Description
when in single clock mode. All accesses are initiated
when in single clock mode.
[7:4]
1
controls D
.
1
controls D
[17:9]
[x:0]
[17:9].
, BWS
are automatically tri-stated.
2
controls D
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
[26:18]
Page 6 of 28
and BWS
3