CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 22

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05565 Rev. *E
Switching Characteristics
t
t
t
t
t
t
Set-up Times
t
t
t
t
Hold Times
t
t
t
t
Notes:
Parameter
24. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
25. This part has a voltage regulator internally; t
26. For DQ0 data signal on CY7C1528V18 device, t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
Cypress
[26]
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
can be initiated.
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
V
Access
K Clock and C Clock Cycle
Time
Input Clock (K/K and C/C)
HIGH
Input Clock (K/K and C/C)
LOW
K Clock Rise to K Clock Rise
and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock
Rise (rising edge to rising
edge)
Address Set-up to K Clock
Rise
Control Set-up to Clock
(K, K) Rise (LD, R/W)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
BWS
D
(K and K) Rise
Address Hold after K Clock
Rise
Control Hold after Clock
(K and K) Rise (LD, R/W)
Double Data Rate Control
Hold after Clock (K and K)
Rise (BWS
BWS
D
(K and K) Rise
DD
[X:0]
[X:0]
(Typical) to the first
3
3
Hold after Clock
0
Set-up to Clock
)
)
, BWS
[25]
Description
Over the Operating Range
0
POWER
, BWS
1
, BWS
SD
is the time that the power needs to be supplied above V
is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
1
, BWS
2
,
2
,
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
3.30 5.25 3.60 5.25
1.32
1.32
1.49
0.30
0.30
0.4
0.3
0.4
300 MHz
0.0
0.4
0.3
0.4
1
[23, 24]
1.45
–
–
–
–
–
–
–
–
–
–
0.30
0.30
278 MHz
1.4
1.4
1.6
0.0
0.4
0.4
0.3
0.3
0.4
0.4
1
1.55
–
–
–
–
–
–
–
–
–
–
0.35
0.35
0.35
0.35
250 MHz
4.0
1.6
1.6
1.8
0.0
0.5
0.5
0.5
0.5
1
DD
minimum initially before a read or write operation
6.3
1.8
–
–
–
–
–
–
–
–
–
–
–
200 MHz
5.0
2.0
2.0
2.2
0.0
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
1
7.9
2.2
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
–
–
–
–
–
–
–
–
–
–
–
6.0
2.4
2.4
2.7
0.0
0.7
0.7
0.5
0.5
0.7
0.7
0.5
0.5
167 MHz
1
Page 22 of 28
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns