CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05565 Rev. *E
Application Example
Truth Table
Linear Burst Address Table
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Write Cycle:
Load address; wait one
cycle; input write data on
four consecutive K and K
rising edges.
Read Cycle:
Load address; wait one
and a half cycle; read data
on four consecutive C and
C rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes:
MASTER
2. The above application shows 2 DDR-II being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
4. Device will power-up deselected and the outputs in a tri-state condition.
5. On CY7C1519V18 and CY7C1521V18, “A1” represents address location latched by the devices when transaction was initiated and A2, A3, A4 represents the
6. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
9. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. NWS
ASIC)
(CPU
BUS
First Address (External)
addresses sequence in the burst. On CY7C1517V18, “A1” represents A + ‘00’, A2 represents A + ‘01’, “A3” represents A + ‘10’ and “A4” represents A + ‘11’.
charging symmetrically.
of a write cycle, as long as the set-up and hold requirements are achieved.
or
Operation
Return CLK#
Source CLK#
Cycle Start#
Return CLK
Source CLK
X..X00
X..X01
X..X10
X..X11
Addresses
[3, 4, 5, 6, 7, 8]
R/W#
DQ
R = 50ohms
[2]
L-H
L-H
L-H
Stopped X
K
Vterm = 0.75V
Vterm = 0.75V
DQ
Second Address (Internal)
A
(CY7C1519V18 and CY7C1521V18)
L
L
H
LD R/W
LD#
SRAM#1
↑
L
H
X
X
R/W#
X..X00
X..X01
X..X10
X..X11
represents rising edge.
C C#
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ D(A3) at K(t + 2) ↑ D(A4) at K(t + 2) ↑
Q(A1) at C(t + 1) ↑ Q(A2) at C(t + 2) ↑ Q(A3) at C(t + 2) ↑ Q(A4) at C(t + 3) ↑
High-Z
Previous State
CQ/CQ#
K
ZQ
DQ
K#
R = 250ohms
Third Address (Internal)
High-Z
Previous State
0
, NWS
1,
DQ
X..X10
X..X00
X..X01
X..X11
BWS
0
, BWS
DQ
A
1,
BWS
High-Z
Previous State
LD#
2
, BWS
SRAM#2
R/W#
DQ
3
Fourth Address (Internal)
can be altered on different portions
C C#
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
CQ/CQ#
K
High-Z
Previous State
X..X11
X..X00
X..X01
X..X10
ZQ
K#
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DQ
R = 250ohms