C8051F521-IMR Silicon Labs, C8051F521-IMR Datasheet
C8051F521-IMR
Specifications of C8051F521-IMR
Related parts for C8051F521-IMR
C8051F521-IMR Summary of contents
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Analog Peripherals - 12-Bit ADC • Programmable throughput up to 200 ksps • 6/16 external inputs • Data dependent windowed interrupt generator • Built-in temperature sensor - Comparator • Programmable hysteresis and response time • Configurable as wake-up ...
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C8051F52x/F53x 2 Rev. 1.4 ...
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Table of Contents 1. System Overview ..................................................................................................... 13 1.1. Ordering Information.......................................................................................... 14 1.2. CIP-51™ Microcontroller ................................................................................... 18 1.2.1. Fully 8051 Compatible Instruction Set ...................................................... 18 1.2.2. Improved Throughput................................................................................ 18 1.2.3. Additional Features ................................................................................... 18 1.2.4. On-Chip Debug Circuitry ........................................................................... 18 ...
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C8051F52x/F53x 8.3.2. Stop Mode................................................................................................. 90 8.3.3. Suspend Mode .......................................................................................... 90 9. Memory Organization and SFRs............................................................................. 92 9.1. Program Memory............................................................................................... 92 9.2. Data Memory ..................................................................................................... 93 9.3. General Purpose Registers ............................................................................... 93 9.4. Bit Addressable Locations ................................................................................. 93 9.5. Stack ............................................................................................................ ...
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External Crystal Example...................................................................... 139 14.2.3. External RC Example............................................................................ 141 14.2.4. External Capacitor Example.................................................................. 141 14.3. System Clock Selection................................................................................. 143 15. UART0 ................................................................................................................... 144 15.1. Enhanced Baud Rate Generation.................................................................. 145 15.2. Operational Modes ........................................................................................ 146 15.2.1. 8-Bit UART ............................................................................................ 146 ...
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C8051F52x/F53x 19. Programmable Counter Array (PCA0)................................................................ 195 19.1. PCA Counter/Timer ....................................................................................... 196 19.2. Capture/Compare Modules ........................................................................... 197 19.2.1. Edge-triggered Capture Mode............................................................... 198 19.2.2. Software Timer (Compare) Mode.......................................................... 199 19.2.3. High Speed Output Mode...................................................................... 200 19.2.4. Frequency Output Mode ....................................................................... 201 ...
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List of Figures Figure 1.1. C8051F53xA/F53x-C Block Diagram .................................................... 16 Figure 1.2. C8051F52xA/F52x-C Block Diagram .................................................... 16 Figure 1.3. C8051F53x Block Diagram (Silicon Revision A) ................................... 17 Figure 1.4. C8051F52x Block Diagram (Silicon Revision A) ................................... 17 Figure 1.5. Development/In-System ...
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C8051F52x/F53x Figure 13.5. Crossbar Priority Decoder with No Pins Skipped (DFN 10) .............. 124 Figure 13.6. Crossbar Priority Decoder with Some Pins Skipped (DFN 10) ......... 125 Figure 14.1. Oscillator Diagram ............................................................................. 135 Figure 14.2. 32 kHz External Crystal Example ...
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List of Tables Table 1.1. Product Selection Guide (Recommended for New Designs) .................. 14 Table 1.2. Product Selection Guide (Not Recommended for New Designs) ........... 15 Table 1.3. Operating Modes Summary .................................................................... 21 Table 2.1. Absolute Maximum Ratings .................................................................... 25 ...
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C8051F52x/F53x List of Registers SFR Definition 4.4. ADC0MX: ADC0 Channel Select ................................................... 64 SFR Definition 4.5. ADC0CF: ADC0 Configuration ..................................................... 65 SFR Definition 4.6. ADC0H: ADC0 Data Word MSB .................................................... 66 SFR Definition 4.7. ADC0L: ADC0 Data Word LSB ..................................................... ...
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SFR Definition 13.13. P0SKIP: Port0 Skip .................................................................. 134 SFR Definition 13.14. P1MAT: Port1 Match ............................................................... 134 SFR Definition 13.15. P1MASK: Port1 Mask .............................................................. 134 SFR Definition 14.1. OSCICN: Internal Oscillator Control .......................................... 137 SFR Definition 14.2. OSCICL: Internal Oscillator Calibration ...
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C8051F52x/F53x SFR Definition 19.2. PCA0MD: PCA Mode ................................................................ 207 SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 208 SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 209 SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte ..................................... 209 SFR Definition ...
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System Overview The C8051F52x/F52xA/F53x/F53xA family of devices are fully integrated, low power, mixed-signal system- on-a-chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. High-speed pipelined 8051-compatible microcontroller core ( ...
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... ADC Internal Voltage Reference and Temperature Sensor One Analog Comparator Table 1.1 shows the features that differentiate the devices in this family. Table 1.1. Product Selection Guide (Recommended for New Designs) C8051F520-C- C8051F521-C- C8051F523-C- C8051F524-C- C8051F526-C-IM 2 ...
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... Table 1.2. Product Selection Guide (Not Recommended for New Designs) C8051F520- C8051F520A-IM C8051F521- C8051F521A-IM C8051F523- C8051F523A-IM C8051F524- C8051F524A-IM C8051F526- C8051F526A-IM C8051F527- C8051F527A-IM C8051F530- C8051F530A-IM C8051F531- C8051F531A-IM C8051F533- C8051F533A-IM The part numbers in Table 1.2 are not recommended for new designs. Instead, select the corresponding part number from Table 1 ...
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C8051F52x/F53x Power On CIP-51 8051 Reset Controller Core Reset Byte Flash Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator ...
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Power On CIP-51 8051 Reset Controller Core Reset Byte Flash Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator Figure ...
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C8051F52x/F53x 1.2. CIP-51™ Microcontroller 1.2.1. Fully 8051 Compatible Instruction Set The C8051F52x/F52xA/F53x/F53xA devices use Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop ...
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USB debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply. The development kit requires a computer with Windows installed. As shown ...
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C8051F52x/F53x 1.3. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...
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Operating Modes The C8051F52x/F52xA/F53x/F53xA devices have four operating modes: Active (Normal), Idle, Suspend, and Stop. Active mode occurs during normal operation when the oscillator and peripherals are active. Idle mode halts the CPU while leaving the peripherals and internal ...
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C8051F52x/F53x 1.5. 12-Bit Analog to Digital Converter The C8051F52x/F52xA/F53x/F53xA devices include an on-chip 12-bit SAR ADC with a maximum through- put of 200 ksps. The ADC system includes a configurable analog multiplexer that selects the positive ADC input, which is ...
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Programmable Comparator C8051F52x/F52xA/F53x/F53xA devices include a software-configurable voltage comparator with an input multiplexer. The comparator offers programmable response time and hysteresis and an output that is optionally available at the Port pins: a synchronous “latched” output (CP0). The comparator ...
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C8051F52x/F53x 1.9. Port Input/Output C8051F52x/F52xA/F53x/F53xA devices include I/O pins. Port pins are organized as two byte- wide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as ...
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Electrical Characteristics 2.1. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under Bias Storage Temperature Voltage on V with Respect to GND REGIN Voltage on V with Respect to GND DD Voltage on XTAL1 with Respect ...
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C8051F52x/F53x 2.2. Electrical Characteristics Table 2.2. Global DC Electrical Characteristics –40 to +125 °C, 25 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter 1 Supply Input Voltage (V ) REGIN ) Digital Supply Voltage ...
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Table 2.2. Global DC Electrical Characteristics –40 to +125 °C, 25 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) 3,4 Idle I DD ...
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C8051F52x/F53x Table 2.3. ADC0 Electrical Characteristics 1.5 V (REFSL=0), –40 to +125 °C unless otherwise specified. DD REF Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity 1 Offset Error Full Scale Error Dynamic Performance ...
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Table 2.4. Temperature Sensor Electrical Characteristics 1.5 V (REFSL=0), –40 to +125 °C unless otherwise specified. DD REF Parameter 1 Linearity 1 Gain 2 Gain Error 1 Offset Temp = 0 °C 2 Offset ...
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C8051F52x/F53x Table 2.6. Voltage Regulator Electrical Specifications V = 2.1 or 2.6 V; –40 to +125 °C unless otherwise specified. DD Parameter Input Voltage Range (V ) C8051F52x/53x REGIN C8051F52xA/53xA C8051F52x-C/53x-C Dropout Voltage (V ) Output Current = 1-50 mA ...
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Table 2.7. Comparator Electrical Characteristics = 2.7–5.25 V, –40 to +125 °C unless otherwise noted. V REGIN All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Response Time: CP0+ – CP0– = 100 mV 1 Mode ...
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C8051F52x/F53x Table 2.8. Reset Electrical Characteristics –40 to +125 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Impedance Missing Clock Detector Timeout 1 Reset Time Delay (T ) ...
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Table 2.9. Flash Electrical Characteristics V = 1.8 to 2.75 V; –40 to +125 ºC unless otherwise specified DD Parameter Flash Size ’F520/0A/1/1A and ’F530/0A/1/1A ’F523/3A/4/4A and ’F533/3A/4/4A ’F526/6A/7/7A and ’F536/6A/7/7A Endurance V DD RST-HIGH Erase Cycle ...
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C8051F52x/F53x Table 2.11. Internal Oscillator Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings. DD Parameter 1 Oscillator Frequency IFCN = 111b VDD > VREGMIN IFCN = 111b VDD < VREGMIN ...
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Pinout and Package Definitions RST/C2CK 1 P0.0/V 2 REF GND REGIN RST/C2CK 1 P0.0/V 2 REF GND REGIN Figure 3.1. DFN-10 Pinout Diagram (Top View) C8051F52x/F53x 10 ...
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C8051F52x/F53x Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10) Name Pin Numbers Type ‘F52xA ‘F52x ‘F52x-C RST I/O C2CK D I/O P0. I REF ...
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Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10) (Continued) Name Pin Numbers Type ‘F52xA ‘F52x ‘F52x-C P0.3/TX*/ — I I/O XTAL2 P0 I/O or XTAL1 A In P0.1/ ...
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C8051F52x/F53x Figure 3.2. DFN-10 Package Diagram Table 3.2. DFN-10 Package Diagram Dimensions Dimension aaa bbb ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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Figure 3.3. DFN-10 Landing Diagram Table 3.3. DFN-10 Landing Diagram Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the ...
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C8051F52x/F53x P0 P0.3 P0 P0.4/TX RST/C2CK 3 18 P0.5/RX P0.0 P0.6/C2D REF GND 5 16 P0.7/XTAL1 P1.0/XTAL2 P1.1 REGIN 8 13 P1.2/CNVSTR P1 P1.3 P1.6 ...
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Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) (Continued) Name Pin Numbers Type ‘F53xA ‘F53x ‘F53x REGIN P1.5 ...
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C8051F52x/F53x Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) (Continued) Name Pin Numbers Type ‘F53xA ‘F53x ‘F53x-C P0.4/TX* 19 — P0.4/RX* — I P0.3 20 — D ...
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Figure 3.5. TSSOP-20 Package Diagram Table 3.5. TSSOP-20 Package Diagram Dimensions Symbol Min A — A1 0.05 A2 0.80 b 0.19 c 0. 4.30 L 0.45 1 0° aaa bbb ddd Notes: 1. All dimensions ...
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C8051F52x/F53x Figure 3.6. TSSOP-20 Landing Diagram Table 3.6. TSSOP-20 Landing Diagram Dimensions Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 ...
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RST/C2CK 1 P0.0/V 2 REF C8051F53xA/53x-C GND 3 Top View GND V 5 REGIN RST/C2CK 1 P0.0/V 2 REF C8051F53x GND 3 Top View GND V 5 REGIN Figure 3.7. QFN-20 Pinout Diagram (Top ...
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C8051F52x/F53x Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20) Name Pin Numbers Type ‘F53xA ‘F53x ‘F53x-C RST I/O C2CK D I/O P0. I REF ...
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Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20) (Continued) Name Pin Numbers Type ‘F53xA ‘F53x ‘F53x-C P1. I XTAL2 D I/O P0. I/O or XTAL1 A In P0.6/ ...
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C8051F52x/F53x Figure 3.8. QFN-20 Package Diagram* *Note: The Package Dimensions are given in Table 3.8, “QFN-20 Package Diagram Dimensions,” on page 49. 48 Rev. 1.4 ...
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Table 3.8. QFN-20 Package Diagram Dimensions Dimension MIN A 0.80 A1 0. 2.55 L 0.30 L1 0.00 aaa — bbb — ddd — eee — Z — Y — Notes: 1. All ...
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C8051F52x/F53x Figure 3.9. QFN-20 Landing Diagram* Note: The Landing Dimensions are given in Table 3.9, “QFN-20 Landing Diagram Dimensions,” on page 51. 50 Rev. 1.4 ...
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Table 3.9. QFN-20 Landing Diagram Dimensions Symbol Min C1 3. 0.20 X2 2.75 Y1 0.65 Y2 2.75 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is ...
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C8051F52x/F53x 4. 12-Bit ADC (ADC0) The ADC0 on the C8051F52x/F52xA/F53x/F53xA Family consists of an analog multiplexer (AMUX0) with 16/6 total input selections, and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with inte- grated track-and-hold, programmable window detector, programmable gain, and ...
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Temperature Sensor An on-chip temperature sensor is included on the C8051F52x/F52xA/F53x/F53xA devices which can be directly accessed via the ADC0 multiplexer. To use ADC0 to measure the temperature sensor, the ADC multiplexer channel should be configured to connect to ...
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C8051F52x/F53x 4.3. ADC0 Operation In a typical system, ADC0 is configured using the following steps gain adjustment is required, refer to Section “4.4. Selectable Gain” on page 60. 2. Choose the start of conversion source. 3. Choose ...
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Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ...
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C8051F52x/F53x Convert Start Time F S1 ADC0 State AD0INT Flag Time F S1 ADC0 State AD0INT Flag Key F Sn Figure 4.4. 12-Bit ADC Tracking Mode Example 56 Pre-Tracking Mode ... S2 S12 S13 F Convert Post-Tracking or Dual-Tracking Modes ...
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Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between con- versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, ...
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C8051F52x/F53x System Clock Convert Start (AD0BUSY or Timer Overflow) Post-Tracking Powered Power-Up AD0TM = 01 Down and Idle AD0EN = 0 Dual-Tracking Powered Power-Up AD0TM = 11 Down and Track AD0EN = 0 AD0PWR Post-Tracking AD0TM = 01 Idle T ...
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Output Conversion Code The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output ...
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C8051F52x/F53x 4.3.6. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for ...
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Calculating the Gain Value The ADC0 selectable gain feature is controlled by 13 bits in three registers. ADC0GNH contains the 8 upper bits of the gain value and ADC0GNL contains the 4 lower bits of the gain value. The ...
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C8051F52x/F53x For example, the initial example in this section requires a gain of 0.44 to convert 5 V full scale to 2.2 V full scale. Using Equation 4.3: GAIN = If GAINADD is set to 1, this makes the equation: ...
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Gain Register Definition 4.1. ADC0GNH: ADC0 Selectable Gain High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of Selectable Gain Word. Gain Register Definition 4.2. ADC0GNL: ADC0 Selectable Gain Low Byte R/W R/W R/W GAINL[3:0] Bit7 Bit6 Bit5 ...
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C8051F52x/F53x SFR Definition 4.4. ADC0MX: ADC0 Channel Select R/W R/W R Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AD0MX4–0: AMUX0 Positive Input Selection AD0MX4–0 ADC0 Input Channel 00000 P0.0 00001 P0.1 ...
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SFR Definition 4.5. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held ...
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C8051F52x/F53x SFR Definition 4.6. ADC0H: ADC0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC0 Data Word High-Order Bits. For AD0LJST = 0 and AD0RPT as follows: 00: Bits 3–0 are the upper 4 bits of the 12-bit ...
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SFR Definition 4.8. ADC0CN: ADC0 Control R/W R/W R/W AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active ...
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C8051F52x/F53x SFR Definition 4.9. ADC0TK: ADC0 Tracking Mode Select R/W R/W R/W AD0PWR Bit7 Bit6 Bit5 Bits7–4: AD0PWR3–0: ADC0 Burst Power-Up Time. For BURSTEN = 0: ADC0 power state controlled by AD0EN. For BURSTEN = 1 and AD0EN = 1; ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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C8051F52x/F53x SFR Definition 4.12. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 4.13. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ...
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Window Detector In Single-Ended Mode Figure 4.7 shows two example ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can range from (4095/4096) with respect to GND, and is represented by a ...
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C8051F52x/F53x 5. Voltage Reference The Voltage reference MUX on C8051F52x/F52xA/F53x/F53xA devices is configurable to use an exter- nally connected voltage reference, the internal reference voltage generator, or the V age (see Figure 5.1). The REFSL bit in the Reference Control ...
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Important Note About the V Pin: Port pin P0.0 is used as the external V REF the internal V . When using either an external voltage reference or the internal reference circuitry, P0.0 REF should be configured as an analog ...
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C8051F52x/F53x 6. Voltage Regulator (REG0) C8051F52x/F52xA/F53x/F53xAdevices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the V pin can be as high as 5.25 V. The output can be selected by software to 2.1 V REGIN ...
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SFR Definition 6.1. REG0CN: Regulator Control R/W R/W R REGDIS Reserved — Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable Bit. This bit disables/enables the Voltage Regulator. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: RESERVED. Read = 1b. ...
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C8051F52x/F53x 7. Comparator C8051F52x/F52xA/F53x/F53xA devices include one on-chip programmable voltage comparator. The Comparator is shown in Figure 7.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port ...
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See Section “13.1. Priority Crossbar Decoder” on page 122 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0. 0.25 V without damage ...
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C8051F52x/F53x Note that false rising edges and falling edges can be detected when the comparator is first powered- changes are made to the hysteresis or response time control bits. Therefore recommended that the rising-edge and falling-edge ...
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SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 Bit7 Bit6 Bit5 Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative ...
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C8051F52x/F53x SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W Reserved — CP0RIE Bit7 Bit6 Bit5 Bit7: RESERVED. Read = 0b. Must write 0b. Bit6: UNUSED. Read = 0b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft- ware. The C8051F52x/F52xA/F53x/F53xA family has a superset ...
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... In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire (C2) interface. Note that the re-programmable Flash can also be read and written a single byte at a time by the application software using the MOVC and MOVX instructions ...
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MOVX Instruction and Program Memory The MOVX instruction is typically used to access data stored in XDATA memory space. In the CIP-51, the MOVX instruction can also be used to write or erase on-chip program memory space implemented as ...
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C8051F52x/F53x Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Boolean Manipulation CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit ...
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C8051F52x/F53x Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...
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SFR Definition 8.1. SP: Stack Pointer R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register ...
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C8051F52x/F53x SFR Definition 8.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction). It ...
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SFR Definition 8.5. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 8. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 ...
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C8051F52x/F53x 8.3.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their ...
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SFR Definition 8.7. PCON: Power Control R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Bit7 Bit6 Bit5 Bits7–2: RESERVED. Bit1: STOP: STOP Mode Select. Writing this bit will place the CIP-51 into STOP mode. This bit ...
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C8051F52x/F53x 9. Memory Organization and SFRs The memory organization of the C8051F52x/F52xA/F53x/F53xA is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Data Memory The C8051F52x/F52xA/F53x/F53xAincludes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose regis- ters and scratch pad memory. Either direct ...
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C8051F52x/F53x SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.1 lists the SFRs imple- mented in the CIP-51 System Controller. ...
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Table 9.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0H 0xBE ADC0 ADC0L 0xBD ADC0 ADC0GTH 0xC4 ADC0 Greater-Than ...
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C8051F52x/F53x Table 9.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address OSCICN 0xB2 Internal Oscillator Control OSCXCN 0xB1 External Oscillator Control P0 0x80 Port 0 Latch P0MASK 0xC7 Port 0 ...
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Table 9.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address REF0CN 0xD1 Voltage Reference Control REG0CN 0xC9 Voltage Regulator Control RSTSRC 0xEF Reset Source Configuration/Status SBUF0 0x99 UART0 Data Buffer ...
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C8051F52x/F53x 10. Interrupt Handler The C8051F52x/F52xA/F53x/F53xA family includes an extended interrupt system with two selectable pri- ority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each ...
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RETI, 8 clock cycles to complete the DIV instruction, and 4 clock cycles to execute the LCALL to the ISR. If the CPU ...
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C8051F52x/F53x 10.4. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for ...
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SFR Definition 10.2. IP: Interrupt Priority R R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1b; Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the ...
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C8051F52x/F53x SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 R/W R/W R/W EMAT EREG0 ELIN Bit7 Bit6 Bit5 Bit7: EMAT: Enable Port Match Interrupt. This bit sets the masking of the Port Match interrupt. 0: Disable the Port Match interrupt. ...
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SFR Definition 10.4. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PMAT PREG0 PLIN Bit7 Bit6 Bit5 Bit7: PMAT. Port Match Interrupt Priority Control. This bit sets the priority of the Port Match interrupt. 0: Port Match interrupt set to ...
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C8051F52x/F53x 10.5. External Interrupts The INT0 and INT0 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT0 Polarity) bits in the IT01CF register select active high or ...
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SFR Definition 10.5. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 18.1. “TCON: Timer Control” on page 186 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: INT0 Polarity 0: ...
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C8051F52x/F53x 11. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to ...
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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until ramp time is defined as how fast V RST DD occurs before the device is ...
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C8051F52x/F53x 11.2. Power-Fail Reset / V DD C8051F52x-C/F53x-C devices include two V level-sensitive V monitor (VDDMON1). VDDMON0 is primarily intended for setting a higher threshold to DD allow safe erase or write of Flash memory from firmware. VDDMON1 is used ...
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V two possible ways to handle this transitional period as described below: If using the on-chip regulator (REG0) at the 2.6 V setting (default recommended that user software set the ...
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C8051F52x/F53x 11.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of ...
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Software Reset Software may force a reset by writing the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol- lowing a software forced reset. The state of the RST pin is unaffected by this reset. ...
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C8051F52x/F53x SFR Definition 11.2. RSTSRC: Reset Source R/W R R/W — FERROR C0RSEF Bit7 Bit6 Bit5 Note: Software should avoid read modify write instructions when writing values to RSTSRC. Bit7: UNUSED. Read = 1, Write = don't care. Bit6: FERROR: ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, ...
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C8051F52x/F53x 12.1.2. Flash Erase Procedure The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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C8051F52x/F53x 5. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash. 12.2.3. System Clock 1. If operating from ...
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Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
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C8051F52x/F53x The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...
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SFR Definition 12.1. PSCTL: Program Store R/W Control — — — Bit7 Bit6 Bit5 Bits7–2: UNUSED: Read = 000000b, Write = don’t care. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows ...
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C8051F52x/F53x 13. Port Input/Output Digital and analog resources are available through I/O pins. Port pins are organized as two or one byte-wide Ports. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog ...
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PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 13.2. Port I/O Cell Block Diagram C8051F52x/F53x VREGIN VREGIN (WEAK) GND Rev. 1.4 PORT PAD 121 ...
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C8051F52x/F53x 13.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
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CNVSTR signal, and any selected ADC or comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 13.3 shows the Crossbar Decoder priority with no ...
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C8051F52x/F53x SF Signals DFN10 PIN I TX0 RX0 TX0 RX0 SCK MISO MOSI NSS* LIN-TX LIN_RX CP0 CP0A /SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:5] Port pin potentially assignable to peripheral Special Function Signals are ...
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SF Signals DFN 10 PIN I/O 0 TX0 RX0 TX0 RX0 SCK MISO MOSI NSS* LIN-TX LIN-RX CP0 CP0A /SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:5] = 0x06 Port pin potentially assignable to peripheral Special Function Signals are ...
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C8051F52x/F53x Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to ...
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SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R CP0AE Bit7 Bit6 Bit5 Bit7–6: RESERVED. Read = 00b; Must write 00b. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: ...
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C8051F52x/F53x SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). ...
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In addition to performing general purpose I/O, P0 and P1 can generate a port match event if the logic lev- els of the Port’s input pins match a software controlled value. A port match event is generated if (P0 & ...
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C8051F52x/F53x SFR Definition 13.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding ...
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SFR Definition 13.7. P0MAT: Port0 Match R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P0MAT[7:0]: Port0 Match Value. These bits control the value that unmasked P0 Port pins are compared against. A Port Match event is generated if (P0 & P0MASK) ...
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C8051F52x/F53x SFR Definition 13.9. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n ...
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SFR Definition 13.11. P1MDOUT: Port1 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n ...
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C8051F52x/F53x SFR Definition 13.13. P0SKIP: Port0 Skip R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ...
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Oscillators C8051F52x/F52xA/F53x/F53xA devices include a programmable internal oscillator, an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 14.1. The system clock (SYSCLK) can be derived ...
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C8051F52x/F53x 14.1.1. Internal Oscillator Suspend Mode When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys- tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will ...
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SFR Definition 14.1. OSCICN: Internal Oscillator Control R/W R/W R/W IOSCEN1 IOSCEN0 SUSPEND Bit7 Bit6 Bit5 Bits7–6: IOSCEN[1:0]: Internal Oscillator Enable Bits. 00: Oscillator Disabled. 01: Reserved. 10: Reserved. 11: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode. ...
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C8051F52x/F53x SFR Definition 14.2. OSCICL: Internal Oscillator Calibration R R/W R/W — Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b. Write = don’t care. Bits6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. On C8051F52x/53x devices, ...
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External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...
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C8051F52x/F53x Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data sheet when completing these calculations. The equation for determining the load capacitance for two capacitors is: Where: C and C are the ...
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External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however ...
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C8051F52x/F53x SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Reserved Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. ...
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System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up ...
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C8051F52x/F53x 15. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section ...
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Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in ...
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C8051F52x/F53x 15.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. RS-232 Figure 15.3. UART Interconnect Diagram 15.2.1. 8-Bit UART ...
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UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data ...
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C8051F52x/F53x 15.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, ...
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SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit ...
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C8051F52x/F53x SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data ...
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Enhanced Serial Peripheral Interface (SPI0) The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas- ters ...
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C8051F52x/F53x 16.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 16.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
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SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
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C8051F52x/F53x Master Device 1 Figure 16.2. Multiple-Master Mode Connection Diagram Master Device Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram 16.3. SPI0 Slave Mode Operation ...
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The shift register contents are locked after the slave detects the first edge of SCK. Writes to SPI0DAT that occur after the first SCK edge will be held in the TX latch until the end of the current transfer. When ...
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C8051F52x/F53x 16.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to ...
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SFR Definition 16.1. SPI0CFG: SPI0 Configuration R R/W R/W SPIBSY MSTEN CKPHA Bit7 Bit6 Bit5 Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or Slave Mode). ...
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C8051F52x/F53x SFR Definition 16.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF Bit7 Bit6 Bit5 Bit7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are ...
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SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. ...
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C8051F52x/F53x SFR Definition 16.4. SPI0DAT: SPI0 Data R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the ...
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SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.6. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
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C8051F52x/F53x NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.8. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...
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Table 16.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing* (See Figure 16.6 and Figure 16.7) SCK High Time T MCKH SCK Low Time T MCKL MISO Valid to SCK Sample Edge T MIS SCK Sample Edge to MISO ...
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C8051F52x/F53x 17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A) Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto- col. For more information about the LIN protocol, including specifications, please refer to the LIN consor- tium (http://www.lin-subbus.org/). LIN is ...
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Software Interface with the LIN Peripheral The selection of the mode (Master or Slave) and the automatic baud rate feature are done though the LIN0 Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the two ...
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C8051F52x/F53x Table 17.1. Baud-Rate Calculation Variable Ranges prescaler multiplier Important: The minimum system clock (SYSCLK) to operate the LIN peripheral is 8 MHz. Use the following equations to calculate the values for the variables for the baud-rate equation: prescaler = ...
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The following code programs the interface in Master mode, using the Enhanced Checksum and enables the interface to operate at 19200 bits/sec using a 24 MHz system clock. LIN0CF = 0x80;// Activate the interface LIN0CF |= 0x40;// Set the node ...
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C8051F52x/F53x 17.2.4. Baud Rate Calculations—Automatic Mode If the LIN peripheral is configured for slave mode, only the prescaler and divider need to be calculated: prescaler divider The following example calculates the values of these variables for a 24 MHz system ...
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LIN Master Mode Operation The master node is responsible for the scheduling of messages and sends the header of each frame, con- taining the SYNCH BREAK FIELD, SYNCH FIELD and IDENTIFIER FIELD. The steps to schedule a mes- sage ...
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C8051F52x/F53x 17.4. LIN Slave Mode Operation When the device is configured for slave mode operation, it must wait for a command from a master node. Access from the firmware to data buffer and ID registers of the LIN peripheral is ...
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The same applies to changes in the LIN interface mode from slave mode to master mode and from master mode to slave mode. 17.5. Sleep Mode and Wake-Up To reduce the system’s power consumption, the LIN Protocol Specification ...
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C8051F52x/F53x 17.7. LIN Registers The following Special Function Registers (SFRs) are available: 17.7.1. LIN Direct Access SFR Registers Definition SFR Definition 17.1. LINADDR: Indirect Address Register R/W R/W R/W Bit7 Bit6 Bit5 Bit7–0: LINADDR7-0: LIN Indirect Address Register Bits. This ...
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SFR Definition 17.3. LINCF Control Mode Register R/W R/W R/W LINEN MODE ABAUD Bit7 Bit6 Bit5 Bit7: LINEN: LIN Interface Enable bit 0: LIN0 is disabled. 1: LIN0 is enabled. Bit6: MODE: LIN Mode Selection 0: LIN0 operates in Slave ...
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C8051F52x/F53x 17.7.2. LIN Indirect Access SFR Registers Definition Table 17.4. LIN Registers* (Indirectly Addressable) Name Address Bit7 Bit6 LIN0DT1 0x00 LIN0DT2 0x01 LIN0DT3 0x02 LIN0DT4 0x03 LIN0DT5 0x04 LIN0DT6 0x05 LIN0DT7 0x06 LIN0DT8 0x07 LIN0CTRL 0x08 STOP(s) SLEEP(s) LIN0ST 0x09 ...
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SFR Definition 17.5. LIN0DT2: LIN0 Data Byte 2 R/W R/W R/W Bit7 Bit6 Bit5 Bit7–0: LIN0DT2: LIN Data Byte 2. Serial Data Byte 2 that is received or transmitted across the LIN interface. SFR Definition 17.6. LIN0DT3: LIN0 Data Byte ...
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C8051F52x/F53x SFR Definition 17.8. LIN0DT5: LIN0 Data Byte 5 R/W R/W R/W Bit7 Bit6 Bit5 Bit7–0: LIN0DT5: LIN Data Byte 5. Serial Data Byte 5 that is received or transmitted across the LIN interface. SFR Definition 17.9. LIN0DT6: LIN0 Data ...
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SFR Definition 17.12. LIN0CTRL: LIN0 Control Register STOP SLEEP TXRX Bit7 Bit6 Bit5 Bit7: STOP: Stop Communication Processing Bit (slave mode only). This bit set by the application to block the processing of the ...
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C8051F52x/F53x SFR Definition 17.13. LIN0ST: LIN0 STATUS Register ACTIVE IDLTOUT ABORT Bit7 Bit6 Bit5 Bit7: ACTIVE: LIN Bus Activity Bit transmission activity detected on the LIN bus. 1: Transmission activity detected on the LIN bus. ...
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SFR Definition 17.14. LIN0ERR: LIN0 ERROR Register Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b. Write = don’t care. Bit4: SYNCH: Synchronization Error Bit (slave mode only error with the SYNCH FIELD has been detected. ...
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C8051F52x/F53x SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register R/W R/W R/W ENHCHK - - Bit7 Bit6 Bit5 Bit7: ENHCHK: Checksum Selection Bit. 0: Use the classic, specification 1.3 compliant checksum. Checksum covers the data bytes. 1: Use the enhanced, ...
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SFR Definition 17.17. LIN0MUL: LIN0 Multiplier Register R/W R/W R/W PRESCL[1:0] Bit7 Bit6 Bit5 Bit7–6: PRESCL1–0: LIN Baud Rate Prescaler Bits. These bits are the baud rate prescaler bits. Bit5–1: LINMUL4–0: LIN Baud Rate Multiplier Bits. These bits are the ...
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C8051F52x/F53x 18. Timers Each MCU includes three counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with other device peripherals or for general purpose use. These timers ...
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When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see SFR Definition 18.3). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) ...
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C8051F52x/F53x 18.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for ...
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Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
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C8051F52x/F53x SFR Definition 18.1. TCON: Timer Control R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically ...
Page 187
SFR Definition 18.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT0 logic level. 1: Timer 1 enabled only when ...
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C8051F52x/F53x SFR Definition 18.3. CKCON: Clock Control R/W R/W R/W — — T2MH Bit7 Bit6 Bit5 Bit7–6: RESERVED. Read = 0b; Must write 0b. Bit5: T2MH: Timer 2 High Byte Clock Select. This bit selects the clock supplied to the ...
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SFR Definition 18.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 18.5. TL1: Timer 1 Low ...
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C8051F52x/F53x 18.2. Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines ...
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Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH ...
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C8051F52x/F53x 18.2.3. External Capture Mode Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4) and ...
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SFR Definition 18.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...
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C8051F52x/F53x SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 18.10. ...
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Programmable Counter Array (PCA0) The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module ...
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C8051F52x/F53x 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function ...
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C8051F52x/F53x 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...
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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
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C8051F52x/F53x 19.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, ...