C8051F521-IMR Silicon Labs, C8051F521-IMR Datasheet - Page 211

• Manufacturer Part Number: C8051F521-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F521-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

20.2. Reset Pin Behavior
The reset behavior differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices. The dif-
ferences affect the state of the RST pin during a VDD Monitor reset.
On Revision A devices, a V
Revision C devices, a V
tion.
20.3. Reset Time Delay
The reset time delay differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A devices, the reset time delay will be as long as 80 ms following a power-on reset, meaning
it can take up to 80 ms to begin code execution. Subsequent resets will not cause the long delay. On Revi-
sion B and Revision C devices, the startup time is around 350 µs, specified as T
“Reset Electrical Characteristics,” on page 32.
20.4. V
The number of V
C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, the only V
(VDDMON0). On these devices, the V
Here, V
tics,” on page 32. The maximum V
the device to be released from reset before V
Revision C devices include two V
V
ramp time is defined as how fast V
Electrical Characteristics,” on page 32 as the threshold of the new level-sensitive V
(VDDMON1). This new V
spective of the length of the V
Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for
DD
monitor (VDDMON1). See Section 11.2 on page 108 for more details. On these devices, the V
recommendations related to minimum V
RST
DD
is the V
Monitors and V
DD
RST-LOW
monitors and definition of “V
First character of
silicon revision
the trace code
DD
identifies the
DD
Monitor reset will pull the RST pin low for the duration of the brownout condi-
DD
threshold of VDDMON0 specifed in Table 2.8, “Reset Electrical Characteris-
monitor will hold the device in reset until V
DD
Figure 20.3. Device Package—DFN 10
Monitor reset does not affect the state of the RST pin. On Revision B and
DD
ramp time.
DD
DD
DD
Ramp Time
monitors: a standard V
ramp time for these devices is 1 ms; slower ramp times may cause
DD
ramps from 0 V to V
ramp time is defined as how fast V
DD
. 
DD
reaches the V
Rev. 1.4
DD
ramp time” differs between the silicon revisions of
DD
monitor present is the standard V
DD
RST1
RST-LOW
monitor (VDDMON0) and a level-sensitive
. V
RST1
C8051F52x/F53x
level.
DD
is specified in Table 2.8, “Reset
reaches the V
DD
ramps from 0 V to V
PORDELAY
RST1
in Table 2.8,
DD
DD
level irre-
monitor
monitor
RST
211
DD
.