C8051F521-IMR Silicon Labs, C8051F521-IMR Datasheet - Page 144

• Manufacturer Part Number: C8051F521-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F521-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
15. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “15.1. Enhanced Baud Rate Generation” on page 145). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte. (Please refer to
ciated with the UART interface.)
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
144
Rate Generator
UART Baud
Section “20. Device Specific Behavior” on page 210
Write to
SBUF
Figure 15.1. UART0 Block Diagram
Rx Clock
Start
Tx Clock
Start
Stop Bit
SBUF
Read
SCON
D
TB8
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
(9 bits)
Tx Control
Rx Control
SBUF
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF
Rev. 1.4
RB8
Load SBUF
Rx IRQ
Tx IRQ
TI
RI
SBUF
Load
Send
Data
Interrupt
Serial
Port
for more information on the pins asso-
TX
RX
Crossbar
Crossbar
Port I/O