C8051F521-IMR Silicon Labs, C8051F521-IMR Datasheet - Page 149

• Manufacturer Part Number: C8051F521-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F521-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

SFR Definition 15.1. SCON0: Serial Port 0 Control
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
S0MODE
R/W
Bit7
S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S0MODE = 0: Checks for valid stop bit.
S0MODE = 1: Multiprocessor Communications Enable.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-
bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service
routine. This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
Bit6
R
-
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
MCE0
R/W
Bit5
REN0
R/W
Bit4
Rev. 1.4
TB80
R/W
Bit3
RB80
R/W
Bit2
C8051F52x/F53x
R/W
TI0
Bit1
SFR Address:
RI0
R/W
Bit0
01000000
Addressable
Reset Value
0x98
Bit
149