C8051F521-IMR Silicon Labs, C8051F521-IMR Datasheet - Page 65

• Manufacturer Part Number: C8051F521-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F521-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

SFR Definition 4.5. ADC0CF: ADC0 Configuration
Note: Round the result up.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Bit0:
R/W
Bit7
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 2.3 on page 28.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the Burst Mode Oscillator, specified in Table 2.3.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
GAINEN: Gain Enable Bit.
Controls the gain programming. For more information of the usage, refer to the following
chapter: Section “4.4. Selectable Gain” on page 60.
AD0SC
R/W
Bit6
=
------------------- - 1
CLK
AD0SC
FCLK
R/W
Bit5
SAR
–
*
R/W
Bit4
or
Rev. 1.4
R/W
Bit3
CLK
SAR
R/W
Bit2
=
AD0RPT
----------------------------
AD0SC
FCLK
C8051F52x/F53x
R/W
Bit1
+
1
GAINEN
R/W
Bit0
SFR Address:
Reset Value
11111000
0xBC
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