FDG314P_Q Fairchild Semiconductor, FDG314P_Q Datasheet - Page 8

• Manufacturer Part Number: FDG314P_Q
• Description: MOSFET SC70-6 P-CH -25V
• Manufacturer: Fairchild Semiconductor

Specifications of FDG314P_Q

• Product Category: MOSFET
• Transistor Polarity: P-Channel
• Drain-source Breakdown Voltage: - 25 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: - 0.65 A
• Resistance Drain-source Rds (on): 1.1 Ohms
• Configuration: Single Quad Drain
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: SC-70-6
• Fall Time: 8 ns
• Forward Transconductance Gfs (max / Min): 0.9 S
• Minimum Operating Temperature: - 55 C
• Power Dissipation: 0.75 W
• Rise Time: 8 ns
• Typical Turn-off Delay Time: 55 ns

© 2006 Fairchild Semiconductor Corporation
FAN5631/FAN5632 Rev. 1.0.2
Block Diagram
Detailed Description
The FAN5631 / FAN5632 switched capacitor DC/DC
converter automatically configures switches to achieve
high efficiency and provides a regulated output voltage
by
modulation (PFM). An internal soft-start circuit prevents
excessive inrush current from the supply. Each switch is
split into three segments. Based on the values of V
V
number of segments used to reduce current spikes.
Step-Down Charge Pump Operation
When V
Figure 15 is enabled. The factor 0.9 is used instead of 1
to account for the effect of resistive losses across the
switches and to accommodate hysteresis in the voltage
detector comparator. Two-phase, non-overlapping clock
signals are generated to drive four switches. When
switches 1 and 3 are on, switches 2 and 4 are off and
C
are off and charge is transferred from C
When V
Figure 16 is enabled. In the 1:1 configuration, switch 3
is always off and the switch 4 is always on. At 1.6V
output setting, the configuration changes from 2:1 to 1:1
at V
at V
OUT
B
is charged. When switches 2 and 4 are on, 1 and 3
IN
IN
, and I
means
=3.06V.
=3.56V. At 1.3V output setting, the change occurs
IN
IN
≥ 2 × V
≥ 2 × V
OUT
of
; an internal circuit determines the
SOFT START
V ref RAMP
VOLTAGE
OUT
OUT
pulse
REF.
/9, the 2:1 configuration shown in
/9, the 1:1 configuration shown in
0.5* INPUT
skipping,
V ref RAMP
OUTPUT
150mV
OUT
1V
FB
FB
IN
-
+
+
-
-
+
+
-
SHORT_CKT.
CONFIGURATION
PULSE_SKIP
pulse
B
UVLO
to C
Figure 14.
OUT
ENABLE
frequency
SHUTDOWN
OSCILLATOR
CONTROL
.
(2MHz)
LOGIC
IN
,
Block Diagram
8
SHUTDOWN
THERMAL
Pulse-skipping PFM and Fractional Switch
Operation
When the regulated output voltage reaches its upper
limit, the switches are turned off and the output voltage
reaches its lower limit. In a step-down 2:1 mode of
operation, with 1.6V output as an example; when the
output reaches about 1.62V (upper limit), the control
logic turns off all switches: switching stops completely.
This is pulse-skipping mode. Since the supply is
isolated from the output, the output voltage drops. Once
the output is dropped to about 1.58V (lower limit), the
device returns to regular switching mode with one
quarter of each switch turning on first. Another quarter
of each switch is turned on if V
regulation by the third charge cycle. Full switch
operation occurs only during star-up or under heavy-
load condition, when half switch operation cannot
achieve regulation within seven charge cycles.
Soft-Start
The soft-start feature limits inrush current when the
device is initially powered up and enabled. The
reference voltage is used to control the rate of the
output voltage ramp-up to its final value. Typical start-up
time is 1ms. Since the rate of the output voltage ramp-
up is controlled by an internally generated slow ramp,
pulse-skipping
automatically limited.
D
R
V
E
R
S
I
occurs
0.25SW1 0.25SW1
0.25SW3
0.25SW2
0.25SW4
and
GND.
0.25SW2
0.25SW3 0.5SW3
0.25SW4 0.5SW4
V IN
inrush
0.5SW1
0.5SW2
OUT
FB
cannot reach
current
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C+
V OUT
C-
is