IS43R16800C-5TL ISSI, Integrated Silicon Solution Inc, IS43R16800C-5TL Datasheet
IS43R16800C-5TL
Specifications of IS43R16800C-5TL
Related parts for IS43R16800C-5TL
IS43R16800C-5TL Summary of contents
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... IS43R16800C IC43R16800C 256Mb Double Data Rate (DDR) Synchronous DRAM Specifications Density: 128M bits Organization 2M words 16 bits 4 banks Package: 66-pin plastic TSOP (II) Lead-free (RoHS compliant) Power supply: VDD, VDDQ 2.5V Data rate: 400Mbps/333Mbps/266Mbps (max.) Four internal banks for concurrent operation Interface: SSTL_2 ...
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... IS43R16800C IC43R16800C Pin Configurations /xxx indicates active low signal. Pin name Function A0 to A11 Address inputs BA0, BA1 Bank select address DQ0 to DQ15 Data-input/output LDQS, UDQS Input and output data strobe /CS Chip select /RAS Row address strobe command /CAS Column address strobe command ...
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... IS43R16800C IC43R16800C Block Diagram CK /CK CKE A0 to A11, BA0, BA1 Mode register /CS /RAS /CAS /WE Integrated Silicon Solution, Inc. — www.issi.com Rev. A 10/13/08 Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and ...
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... Pins Table] Address (A0 to A11) Part number Row address IS43R16800C/IC43R16800C AX0 to AX11 A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged ...
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... IS43R16800C IC43R16800C CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. CKE must be maintained high throughout read or write access ...
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... IS43R16800C IC43R16800C Electrical Specifications All voltages are referenced to VSS (GND). After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS ...
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... IS43R16800C IC43R16800C DC Characteristics 1 ( +70 C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR400] Parameter Symbol Operating current (ACT-PRE) IDD0 Operating current IDD1 (ACT-READ-PRE) Idle power down standby current IDD2P Floating idle standby current IDD2F Quiet idle standby current IDD2Q Active power down standby ...
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... IS43R16800C IC43R16800C Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle banks active. Only one bank is running at tRC = tRC (min.) 8 ...
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... IS43R16800C IC43R16800C AC Characteristics ( +70 C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR400] Parameter Clock cycle time CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS ...
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... IS43R16800C IC43R16800C AC Characteristics (TA = 0°C to +70 C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266] Parameter Clock cycle time ( (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK tAC DQS output access time from CK, /CK DQS to DQ skew ...
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... IS43R16800C IC43R16800C Parameter Symbol Write recovery time tWR Auto precharge write recovery and tDAL precharge time Internal write to Read command tWTR delay Average periodic refresh interval tREF Notes all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘ ...
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... IS43R16800C IC43R16800C Test Conditions Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate CK /CK 12 Symbol Value VREF VDDQ/2 VTT VREF VIH (AC) VREF 0 ...
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... IS43R16800C IC43R16800C Timing Parameter Measured in Clock Cycle tCK Parameter Symbol Write to pre-charge command delay tWPD (same bank) Read to pre-charge command delay tRPD (same bank) Write to read command delay tWRD (to input all data) Burst stop command to write command delay tBSTW ( (CL = 2.5) tBSTW ...
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... IS43R16800C IC43R16800C Command Operation Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal. Command Ignore command No operation Burst stop in read command Column address and read command ...
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... IS43R16800C IC43R16800C Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX11). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) ...
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... IS43R16800C IC43R16800C Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Current state /CS /RAS 1 Precharging Idle Refresh H 3 (auto-refresh Activating Active /CAS /WE Address Command DESL H H NOP H L BST ...
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... IS43R16800C IC43R16800C Current state /CS /RAS /CAS /WE 6 Read Read with auto-pre charge Write Write recovering Integrated Silicon Solution, Inc. — www.issi.com Rev. A 10/13/08 Address Command DESL H NOP L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL DESL ...
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... IS43R16800C IC43R16800C Current state /CS /RAS Write with auto pre-charge Remark: H: VIH. L: VIL. : VIH or VIL Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. 2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. 3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. ...
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... IS43R16800C IC43R16800C Command Truth Table for CKE Current State CKE n – /CS Self-refresh Self-refresh recovery Power down All banks idle Row active H L Remark: H: VIH. L: VIL. : VIH or VIL Note: 1. Self-refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Integrated Silicon Solution, Inc. — ...
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... IS43R16800C IC43R16800C Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 15.6 s. The output buffer becomes high-Z after auto-refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command ...
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... IS43R16800C IC43R16800C Simplified State Diagram Write POWER APPLIED Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 10/13/08 SELF ...
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... IS43R16800C IC43R16800C Operation of the DDR SDRAM Power-up Sequence (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 µs. ...
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... IS43R16800C IC43R16800C Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register define the operating mode. Parameters are set to both through the A0 to the A11 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS] ...
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... IS43R16800C IC43R16800C Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out. Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequence Burst length = 8 Starting Ad Burst length = 4 Starting Ad. Addressing(decimal) Interleave A1 A0 Sequence Addressing(decimal) Sequence Interleave Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS43R16800C IC43R16800C Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued ...
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... IS43R16800C IC43R16800C t0 CK /CK READ Command DQS Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set ...
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... IS43R16800C IC43R16800C Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z ...
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... IS43R16800C IC43R16800C Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output ...
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... IS43R16800C IC43R16800C Command Intervals A Read command to the consecutive Read command Interval Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE t0 CK /CK Command ACT NOP READ Row Column A Address BA DQ ...
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... IS43R16800C IC43R16800C /CK Command ACT NOP Row0 Address BA DQ DQS Bank0 Bank3 Active Active READ to READ Command Interval (different bank READ READ ACT NOP Row1 Column A Column B Column = A Column = B Read Read Bank0 Bank3 Read Read Integrated Silicon Solution, Inc. — www.issi.com t7 t8 ...
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... IS43R16800C IC43R16800C A Write command to the consecutive Write command Interval Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE t0 CK /CK Command ACT NOP Row Column A Address BA DQ DQS Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Integrated Silicon Solution, Inc. — ...
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... IS43R16800C IC43R16800C /CK Command ACT NOP Row0 Address BA DQ DQS Bank0 Active WRITE to WRITE Command Interval (different bank tn+1 ACT NOP WRIT WRIT Row1 Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Write Bank3 Active Integrated Silicon Solution, Inc. — www.issi.com ...
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... IS43R16800C IC43R16800C A Read command to the consecutive Write command interval with the BST command Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command READ BST DM DQ High-Z DQS Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS43R16800C IC43R16800C A Write command to the consecutive Read command interval: To complete the burst operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command WRIT DM DQ in0 DQS Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. ...
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... IS43R16800C IC43R16800C A Write command to the consecutive Read command interval: To interrupt the write operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case ...
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... IS43R16800C IC43R16800C /CK Command WRIT NOP 2 cycle DM DQ in0 DQS /CK Command WRIT DM DQ in0 DQS Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR READ CL=3 in1 in2 in3 Data masked [WRITE to READ delay = 2 clock cycle] ...
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... IS43R16800C IC43R16800C A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued /CK Command NOP NOP READ ...
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... IS43R16800C IC43R16800C A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command /CK Command WRIT DM DQS DQ WRITE to PRECHARGE Command Interval (same bank) ( Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank ...
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... IS43R16800C IC43R16800C Bank active command interval Destination row of the consecutive ACT command Bank Row address address State 1. Same Any ACTIVE 2. Different Any ACTIVE IDLE CK /CK Command ACTV ACT Address ROW Bank0 Active tRRD Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD. ...
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... IS43R16800C IC43R16800C DM Control DM can mask input data products, UDM and LDM can mask the upper and lower byte of input data, respectively. By setting DM to low, data can be written. When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0. ...
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... IS43R16800C IC43R16800C Timing Waveforms Command and Addresses Input Timing Definition CK /CK Command (/RAS, /CAS, /WE, /CS) Address Read Timing Definition tCK /CK CK tCH tRPRE DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) DM Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS43R16800C IC43R16800C Read Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active 42 tRC tRAS tIS tIH ...
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... IS43R16800C IC43R16800C Write Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH tIS tIH /CS tIS tIH tIS tIH /RAS tIS tIH tIS tIH /CAS tIS tIH tIS tIH /WE tIS tIH tIS tIH BA tIS tIH tIS tIH A10 tIS tIH tIS tIH ...
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... IS43R16800C IC43R16800C Mode Register Set Cycle 0 1 /CK CK VIH CKE /CS /RAS /CAS /WE BA Address valid DM High-Z DQS High-Z DQ (output) tRP Precharge If needed Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a DM DQS DQ (output) High-Z DQ (input) Bank 0 Active code code tMRD ...
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... IS43R16800C IC43R16800C Auto-refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Integrated Silicon Solution, Inc. — www.issi.com Rev. A 10/13/ High-Z tRFC Auto Bank 0 Refresh Active Bank 0 Read VIH or VIL 45 ...
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... IS43R16800C IC43R16800C Self-Refresh Cycle /CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) Precharge If needed 46 tIS tIH CKE = low High-Z tRP Self Self refresh refresh exit entry Integrated Silicon Solution, Inc. — www.issi.com tSNR tSRD Bank 0 Bank 0 Active Read CL = 2.5 ...
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... IS43R16800C IC43R16800C ORDERING INFORMATION Commercial Range +70 o Frequency Speed Order Part No. (ns) 200 MHz 5 IS43R16800C-5TL 200 MHz 5 IC43R16800C-5TL 166 MHz 6 IS43R16800C-6TL 166 MHz 6 IC43R16800C-6TL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 10/13/ Package 66-pin TSOP-II, Lead-free 66-pin TSOP-II, Lead-free 66-pin TSOP-II, Lead-free ...
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PACKAGING INFORMATION Plastic TSOP 66-pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Min Ref. Std. 66 No. Leads (N) A — 1.20 — A1 0.05 0.15 A2 ...