IS43R16800C-5TL ISSI, Integrated Silicon Solution Inc, IS43R16800C-5TL Datasheet - Page 18

• Manufacturer Part Number: IS43R16800C-5TL
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43R16800C-5TL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R16800C
IC43R16800C
18
Current state
Write with auto-
pre-charge*
Remark: H: VIH. L: VIL. : VIH or VIL
Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
From command
Read w/AP
Write w/AP
2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
5. The DDR SDRAM is in "Active" state after "Activating" is completed.
6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or
10
off.
output and DQ output circuits are turned off.
issued.
a write with auto-precharge enabled, may be followed by any column command to other banks, as long as
that command does not interrupt the read or write data transfer, and all other related limitations apply.
(E.g. Conflict between READ data and WRITE data must be avoided.)
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
/CS
H
L
L
L
L
L
L
L
To command (different bank, non-
interrupting command)
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
/RAS
H
H
H
H
L
L
L
/CAS /WE
H
H
L
L
H
H
L
H
L
H
L
H
L
Address
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
Minimum delay
(Concurrent AP supported)
BL/2
CL(rounded up)+ (BL/2)
1
1 + (BL/2) + tWTR
BL/2
1
Command
DESL
NOP
BST
READ/READA
WRIT/WRIT A
ACT
PRE, PALL
Integrated Silicon Solution, Inc. — www.issi.com
Operation
NOP
NOP
ILLEGAL
ILLEGAL*
ILLEGAL*
ILLEGAL*
ILLEGAL*
ILLEGAL
14
14
11, 14
11, 14
Units
tCK
tCK
tCK
tCK
tCK
tCK
Next state
Precharging
Precharging
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Rev. A
10/13/08