MT48H4M16LFB4-10 Micron Technology Inc, MT48H4M16LFB4-10 Datasheet - Page 25

• Manufacturer Part Number: MT48H4M16LFB4-10
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE with Auto Precharge
NOTE:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
precharge): When a READ to bank m registers, it will
interrupt a WRITE on bank n, with the data-out
appearing 2 or 3 clocks later, (depending on CAS
latency). The precharge to bank n will begin after
t
bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the
READ to bank m (Figure 29, WRITE With Auto Pre-
charge Interrupted by a READ).
WR is met, where
3. Interrupted by a READ (with or without auto
DQM is LOW.
DQM is LOW.
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
Figure 29: WRITE With Auto Precharge Interrupted by a READ
t
WR begins when the READ to
Internal
States
Internal
States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
BANK n,
Page Active
BANK n
WRITE - AP
COL a
BANK n,
T1
D
BANK n
Page Active
a
COL a
IN
T1
D
a
WRITE with Burst of 4
IN
WRITE with Burst of 4
a + 1
T2
D
NOP
IN
a + 1
T2
D
NOP
IN
25
BANK m,
READ - AP
T3
COL d
BANK m
a + 2
T3
Interrupt Burst, Write-Back
t
D
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
NOP
IN
precharge): When a WRITE to bank m registers, it
will interrupt a WRITE on bank n. The precharge to
bank n will begin after
when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered
one clock prior to a WRITE to bank m (Figure 30,
WRITE With Auto Precharge Interrupted by a
WRITE).
4. Interrupted by a WRITE (with or without auto
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
t
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
T5
NOP
Precharge
t
T5
RP - BANK n
d + 1
NOP
D
IN
T6
D
NOP
OUT
d
DON’T CARE
T6
d + 2
NOP
D
t RP - BANK n
IN
Precharge
DON’T CARE
T7
D
d + 1
NOP
t
t RP - BANK m
OUT
WR is met, where
MOBILE SDRAM
T7
d + 3
NOP
D
t WR - BANK m
IN
©2003 Micron Technology, Inc. All rights reserved.
Write-Back
64Mb: x16
t
WR begins