MT48H8M32LFB5-10 IT Micron Technology Inc, MT48H8M32LFB5-10 IT Datasheet - Page 26

• Manufacturer Part Number: MT48H8M32LFB5-10 IT
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
Figure 28: READ With Auto Precharge Interrupted by a WRITE
Figure 27: READ With Auto Precharge Interrupted by a READ
Internal
States
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
NOTE: DQM is LOW.
COMMAND
COMMAND
ADDRESS
BANK m
ADDRESS
BANK n
BANK m
BANK n
DQM
CLK
DQ
CLK
DQ
1
Active
Page
Page Active
READ - AP
T0
BANK n,
NOP
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
T1
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
OUT
-a+1 from contending with D
T2
NOP
T2
NOP
26
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
NOP
Interrupt Burst, Precharge
OUT
a
CAS Latency = 3 (BANK m)
READ with Burst of 4
BANK m,
WRITE - AP
T4
COL d
T4
BANK m
NOP
D
d
IN
IN
Interrupt Burst, Precharge
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WRITE with Burst of 4
-d at T4.
OUT
a
t
RP - BANK n
T5
T5
NOP
d + 1
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
T6
T6
d + 2
NOP
NOP
D
IN
D
OUT
d
DON’T CARE
DON’T CARE
Idle
T7
t WR - BANK m
T7
d + 3
NOP
NOP
D
t RP - BANK m
IN
Write-Back
Precharge
D
d + 1
OUT
Idle
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY