SDED5-001G-NAT SanDisk, SDED5-001G-NAT Datasheet - Page 55

• Manufacturer Part Number: SDED5-001G-NAT
• Description: IC MDOC H3 1GB FBGA
• Manufacturer: SanDisk

Specifications of SDED5-001G-NAT

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Rev. 1.3
9.6
9.6.1
When using a demux NOR-like interface, connect the control signals as follows:
9.6.2
mDOC H3 can use a multiplexed interface to connect to a multiplexed bus. In this configuration,
mDOC H3 AVD# signal is driven by the host's AVD# signal, and the D[15:0] balls, used for
both address inputs and data, are connected to the host AD[15:0] bus.
This mode is automatically entered when a falling edge is detected on AVD#. This edge must
occur after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read
55
Connecting Control Signals
Demux Interface
• A[16:0] – Connect these signals to the host address signals (see Section 9.10 for
• D[15:0] – Connect these signals to the host data signals (see Section 9.10 for
• OE# (Output Enable) and Write Enable (WE#) – Connect these signals to the host
• CE# (Chip Enable) – Connect this signal to the memory address decoder. Most
• RSTIN# (Power-On Reset In) – Connect this signal to the host active-low Power-On
• ID0 (Chip Identification) – This signal must be connected to VSS if the host uses
• BUSY# (Busy) – This signal indicates when the device is ready for first access after
• DMARQ# (DMA Request) – Output used to control multi-page DMA operations.
• IRQ# (Interrupt Request) – Connect this signal to the host interrupt.
• Lock# (LOCK) – Connect to a logical 0 to prevent the usage of the protection key to
• CLK (Clock) – This input is used to support Burst operation when reading flash data.
Multiplexed Interface
platform-related considerations). The A0 signal may be connected to either the host
CPU A0 signal or to VSS.
platform-related considerations).
RD# and WR# signals, respectively.
RISC/mobile processors include a programmable decoder to generate various Chip
Select (CS) outputs for different memory zones. These CS signals can be
programmed to support different wait states to accommodate mDOC H3 timing
specifications.
Reset signal.
only one mDOC H3. If more than one device is being used, refer to Section 9.9 for
more information on device cascading.
reset. It may be connected to an input port of the host, or alternatively it may be used
to hold the host in a wait-state condition. The later option is required for hosts that
boot from mDOC H3.
Connect this output to the DMA controller of the host platform.
open a protected partition. Connect to logical 1 in order to enable usage of protection
keys.
Refer to Section 9.8 for further information on Burst operation.
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Design Considerations
92-DS-1205-10