SDED5-001G-NAT SanDisk, SDED5-001G-NAT Datasheet - Page 57

• Manufacturer Part Number: SDED5-001G-NAT
• Description: IC MDOC H3 1GB FBGA
• Manufacturer: SanDisk

Specifications of SDED5-001G-NAT

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Rev. 1.3
2.
The following steps are required in order to initiate a DMA operation:
1.
2.
3.
4.
5.
6.
Upon command completion IRQ# will be asserted (it is recommended to use IRQ# when
working with DMA). In case of a failure, less than expected amount of data could be transferred.
In commands that use DMA transfer, IRQ# is activated only at the completion of the whole
command; while in commands that do not use DMA transfer IRQ# is typically activated with
every data transfer.
Default setting of DMARQ# is level and active-low. It can be modified using the flHwConfig
DOC Driver API. For more information see the DOC Driver 1.0 Block Device (BD) Software
Developer Kit (SDK) Developer Guide..
9.8.2 Synchronous Burst Operation
In this mode the host reads full sections of 16-bit words synchronized to the CLK input.
Burst operation is controlled by 5 bit fields in each Burst Mode Control register (one for Burst
read and one for Burst write): BURST_EN, WAIT_STATE, LATENCY, HOLD and LENGTH.
For full details on this register, please refer to Section 7.
Burst Read / Write mode is enabled by setting the BURST_EN bit in each Burst Mode Control
register.
57
Level DMARQ# output is asserted while the data is available for read, or data can be
accepted for write. The EDGE bit is set to 0 for this mode.
If the DMA controller supports an edge-sensitive DMARQ# signal, then initialize the DMA
controller to transfer 512 bytes (or your chosen data block size) upon each DMA request. If
the DMA controller supports a level-sensitive DMARQ# signal, then initialize the DMA
controller to transfer data continuously while DMARQ# is asserted.
Set in the DMA Control register values of EDGE bit, PULSE_WIDTH and DMA polarity
corresponding to settings of the host DMA controller. This can be done only once after
system power-up.
Enable DMA transfer with DMA_EN bit in the DMA control register.
If host DMA controller detects the de-assertion of the DMARQ# signal too late (and
attempts to transfer additional words as a result), then DMARQ# can be configured to be de-
asserted earlier by using the DMA Negation Register.
Program host DMA controller to transfer the same number of sectors as will be given in
following logical command.
Issue the DMA data-transfer read/write command with same number of sectors to transfer as
given in the previous step (prior to this, the device should be instructed to perform transfers
in DMA-mode).
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Design Considerations
92-DS-1205-10