SDED5-001G-NAT SanDisk, SDED5-001G-NAT Datasheet - Page 61
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SDED5-001G-NAT
Manufacturer Part Number
SDED5-001G-NAT
Description
IC MDOC H3 1GB FBGA
Manufacturer
SanDisk
Datasheet
1.SDED7-256M-N9Y.pdf
(86 pages)
Specifications of SDED5-001G-NAT
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-25°C ~ 85°C
Package / Case
115-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SDED5-001G-NAT/Y
Manufacturer:
FAIRCHILD
Quantity:
1
Rev. 1.3
9.10 Platform-Specific Issues
This section discusses hardware design issues for major embedded RISC processor families.
9.10.1 Wait State
Wait states can be implemented only when mDOC H3 is designed in a bus that supports a Wait
state insertion, and supplies a WAIT signal.
9.10.2 Big and Little Endian Systems
mDOC H3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least Significant Byte
(LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the byte lanes, bit
D0 and bit D8 are the least significant bits of their respective byte lanes. mDOC H3 can be
connected to a Big Endian device in one of two ways:
1.
2. If needed, set the SWAP bits in the Endian Control register. This enables byte swapping
9.10.3 Busy Signal
The Busy signal (BUSY#) indicates that mDOC H3 has not yet completed internal initialization.
After reset, BUSY# is asserted while the IPL is downloaded into the internal boot block. Once
the download process is completed, BUSY# is de-asserted. It can be used to delay the first access
to mDOC H3 until it is ready to accept valid cycles.
Note: mDOC H3 does NOT use this signal to indicate that the flash is in busy state (e.g.
9.10.4 Working with 16/32-Bit Systems
mDOC H3 uses a 16-bit data bus and supports 16-bit data access by default. However, it can be
configured to support 32-bit data access mode. This section describes the connections required
for each mode.
The default of the DOC Driver for mDOC H3 is set to work in 16-bit mode. It must be specially
configured to support 32-bit mode. Please see DOC Driver or TrueFFS 7.1 documentation for
further details.
Note: The mDOC H3 data bus must be connected to the Least Significant Bits (LSB) of the
61
Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data
bus so that the byte lanes of the CPU match the byte lanes of mDOC H3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of mDOC H3, and
prevents the DOC Driver from identifying it.
when used with big endian 16-bit hosts.
program, read, or erase).
system.
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Design Considerations
92-DS-1205-10