PCA9550DP,118 NXP Semiconductors, PCA9550DP,118 Datasheet - Page 8

• Manufacturer Part Number: PCA9550DP,118
• Description: IC LED DRIVER BLINKER 8-TSSOP
• Manufacturer: NXP Semiconductors
• Type: LED Blinkerr

Specifications of PCA9550DP,118

• Package / Case: 8-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 2
• Internal Driver: Yes
• Type - Primary: LED Blinker
• Frequency: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Low Level Output Current: 6.5 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 500 uA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Segments: 2
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Pin Count: 8
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3387-2; 935272881118; PCA9550DP-T

NXP Semiconductors
7. Characteristics of the I
PCA9550_5
Product data sheet
7.1.1 START and STOP conditions
7.1 Bit transfer
7.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 7.
Fig 8.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 05 — 13 October 2008
8).
2-bit I
Figure
data valid
data line
stable;
2
C-bus LED driver with programmable blink rates
9).
Figure
allowed
change
of data
7).
STOP condition
mba607
P
PCA9550
© NXP B.V. 2008. All rights reserved.
mba608
SDA
SCL
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