ISO1H802G Infineon Technologies, ISO1H802G Datasheet - Page 8

• Manufacturer Part Number: ISO1H802G
• Description: IC SWITCH HISIDE 8CH DSO-36
• Manufacturer: Infineon Technologies
• Series: ISOFACE™r
• Type: High Sider

Specifications of ISO1H802G

• Input Type: Parallel
• Number Of Outputs: 8
• On-state Resistance: 150 mOhm
• Current - Output / Channel: 700mA
• Current - Peak Output: 1.4A
• Voltage - Supply: 15 V ~ 30 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000386327

condition, a second protection level (T
change the output into a low duty cycle PWM (selective
thermal shutdown with restart) to prevent critical chip
temperatures.
Figure 5
The following figures show the timing for a turn on into
short circuit and a short circuit in on-state. Heating up
of the chip may require several milliseconds,
depending on external conditions.
Figure 6
Figure 7
Datasheet
IN
VOUT
T
IN
VOUT
I
IN
VOUT
I
L
L
J
Normal
operation
Overtemperature detection
Turn on into short circuit, shut down by
overtemperature, restart by cooling
Short circuit in on-state, shut down
I
L(SCp)
Output short to GND
I
L(SCr)
Output short to GND
I
L(SCp)
I
L(SCr)
j
> 135°C) will
t
t
t
t
t
t
t
t
t
8
3.4
3.5
The ISO1H802G contains a serial interface that can be
directly controlled by the microcontroller output ports.
3.5.1
the ISO1H802G by means of the CS pin. Whenever the
pin is in a logic low state, data can be transferred from
the µC.
CS High to low transition:
•Serial input data can be clocked in from then on
•SO changes from high impendance state to logic high
or low state corresponding to the SO bit-state
CS Low to high transition:
•Transfer of SI bits from shift register into output
buffers, if number of clock signals was an integer
multiple of 8
•SO changes from the SO bit-state to high impendance
state
To avoid any false clocking the serial input pin SCLK
should be logic high state during high-to-low transition
of CS. When CS is in a logic high state, any signals at
the SCLK and SI pins are ignored and SO is forced into
a high impedance state. The integrated modulo counter
that counts the number of clocks avoids the take over
of invalid commands caused by a spike on the clock
line or wrong number of clock cycles. A command is
only taken over if after the low-to-high transition of the
CS signal the number of counted clock cycles is an
integer multiple of 8.
SCLK - Serial clock. The system clock pin clocks the
internal shift register of the ISO1H802G. The serial
input (SI) accepts data into the input shift register on the
rising edge of SCLK while the serial output (SO) shifts
the output information out of the shift register on the
falling edge of the serial clock. It is essential that the
SCLK pin is in a logic high state whenever chip select
CS - Chip select. The system microcontroller selects
down by overtemperature, restart by
cooling
Reserved
Serial Interface
SPI Signal Description
Functional Description
Version 2.4, 2009-09-16
ISOFACE
ISO1H802G
TM