L6740L STMicroelectronics, L6740L Datasheet - Page 26

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Output voltage positioning
Note:
6.4
Caution:
Note:
6.5
26/44
this case, simply connect a resistor R
be proportional to the delivered current according to the following relationship:
In case no additional information about the delivered current is requested, the DROOP pin
can be shorted to SGND.
Split between R
Droop effect is minimum (i.e. <50mV over 100A) to simplify the compensation network
design.
CORE section - offset (optional)
The OS pin allows programming a positive offset (V
by connecting a resistor R
programmed by connecting the resistor R
rored and then properly sunk from the FB pin as shown in
programmed as follow:
Offset resistor can be designed by considering the following relationship (R
the Droop effect):
Offset implementation is optional, in case it is not desired, simply short the pin to SGND.
In the above formulas, R
between FB pin and the regulated voltage.
NB section - current reading
L6740L embeds a flexible, fully-differential current sense circuitry for the NB section that is
able to read across low-side MOSFET R
the element. The trans-conductance ratio is issued by the external resistor R
outside the chip between NB_ISEN pin and the low-side drain. The current sense circuit
performs sample and hold of the current information. The current that flows from the
NB_ISEN pin is then given by the following equation (See
R
details.
V
V
R
I
ISEN
DROOP
CORE
ISEN
OS
=
=
resistor is typically designed according to the OC Threshold. See
1.240V
------------------ - R
=
R
---------------- - I
R
V
=
VID R
dsON
ISEN
OS
R
LI
–
⋅
⋅
⋅
DCR
------------ - I
FB_COMP
NB
R
FB
FB
G
⋅
=
(
⋅
I
I
DROOP
OUT
DROOP_NB
FB
and R
OS
has to be considered being the total resistance connected
–
to SGND. The pin is internally fixed at 1.240 V so a current is
I
OS
FB_DROOP
)
LI
to SGND: the resulting voltage drop across R
DS(on)
OS
(Figure
between the pin and SGND: this current is mir-
or across a sense resistor placed in series to
9) is useful in custom designs where the
OS
) for the CORE section output voltage
Figure
Figure
10):
9. Output voltage is then
Section 7.4
FB
ISEN
is be fixed by
placed
L6740L
for
LI
will