L6740L STMicroelectronics, L6740L Datasheet - Page 30

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Output voltage positioning
6.10
6.10.1
30/44
Soft-start
L6740L implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required to the input power supply. In SVI mode, soft-start time is intended as
the time required by the device to set the output voltages to the Pre-PWROK Metal VID.
During this phase, the device increases the reference of the enabled section(s) from zero up
to the programmed reference in closed loop regulation. Soft-start is implemented only when
VCC is above UVLO Threshold and the EN pin is set free. See
the SVI interface and how SVC/SVD are interpreted in this phase.
At the end of the digital soft-start, PWRGOOD signal is set free.
Protections are active during this phase as follow:
Reference is increased with fixed dV/dt; soft-start time depends on the programmed voltage
as follow:
Figure 12. System start-up: SVI (left) and PVI (right)
LS-Less start-up
In order to avoid any kind of negative undershoot on the load side during start-up, L6740L
performs a special sequence in enabling the drivers for both sections: during the soft-start
phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRVx = 0) until the first PWM
pulse. After the first PWM pulse, the PWMx outputs switches between logic “0” and logic “1”
and ENDRVx are set to logic “1”.
This particular sequence avoids the dangerous negative spike on the output voltage that
can happen if starting over a pre-biased output especially when exiting from a CORE-OFF
state.
Low-Side MOSFET turn-on is masked only from the control loop point of view: protections
are still allowed to turn-ON the Low-Side MOSFET in case of overvoltage if needed.
T
SS
[
ms
–
–
–
]
=
Undervoltage is enabled when the reference voltage reaches 0.5 V.
Overvoltage is always enabled according to the programmed threshold (by R
FBDisconnection is enabled.
Target_VID 2.56
⋅
VDD_CORE
PWRGOOD
VDD_NB
EN
Section 5
VDD_NB
for details about
VDD_CORE
PWRGOOD
L6740L
EN
OVP
).