L6740L STMicroelectronics, L6740L Datasheet - Page 37

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L6740L
9
System control loop compensation
The device embeds two separate and independent control loops for CORE and NB section.
The control loop for NB section is a simple voltage-mode control loop with (optional) voltage
positioning featured when DROOP pin is shorted with FB. The control loop for the CORE
section also features a current-sharing loop to equalize the current carried by each of the
configured phases.
The CORE control system can be modeled with an equivalent single-phase converter
whose only difference is the equivalent inductor L/N (where each phase has an L inductor
and N is the number of the configured phases). See
Figure 16. Equivalent control loop for NB and CORE sections
This means that the same analysis can be used for both the sections with the only exception
of the different equivalent inductor value (L = L
CORE section) and the current reading gain (R
the CORE section).
The control loop gain results (obtained opening the loop after the COMP pin):
Where:
●
●
●
●
●
●
The control loop gain for each section is designed in order to obtain a high DC gain to
minimize static error and to cross the 0 dB axes with a constant -20 dB/Dec. slope with the
desired crossover frequency ω
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ω
G
Z
F
LOOP
(s)
Z
FB
R
Z
and the applied load R
Z
Z
A(s) is the error amplifier gain;
PWM
(s)
P
F
L
LL
s ( )
(s) is the equivalent inductor impedance;
(s) is the compensation network impedance;
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
Ref
R
is the equivalent output resistance determined by the droop function;
R
FB_NB
F_NB
=
NB_COMP
=
–
LC
C
----- -
10
F-NB
-------------------------------------------------------------------------------------------------------------------
[
9
Z
) and the zero (ω
P
⋅
s ( )
------------------ -
ΔV
V
PWM
OSC
+
PWM Z
IN
Z
L
s ( )
d V
is the PWM transfer function.
⋅
NB_COMP
]
O
⋅
F
;
s ( )
VID_NB
Z
--------------
T
A s ( )
. Neglecting the effect of Z
F
ESR
L
ESR_NB
s ( )
NB
⋅
C
(
O_NB
R
) is fixed by ESR and the Droop resistance.
+
LL
⎛
⎝
V
1
OUT_NB
+
+
Z
P
----------- -
A s ( )
s ( )
1
)
⎞ R
⎠
NB
Z
DS(on)
⋅
F
(s)
Z
FB
for NB section and L = L
FB
(s)
Figure
/R
System control loop compensation
Ref
ISEN
R
R
F
FB
F
(s), the transfer function has one
COMP
16.
C
for NB section and DCR/R
F
PWM
d V
COMP
CORE
VID_CORE
L
CORE
ESR
C
/N for the
O
/N
V
OUT
G
37/44
for