L6740L STMicroelectronics, L6740L Datasheet - Page 32

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Output voltage monitoring and protections
7.2
32/44
The OV threshold needs to be programmed through the OVP pin. Connecting the OVP pin
to SGND through a resistor R
pin. Since the OVP pin sources a constant I
becomes:
Filter OVP pin with 100 pF(max) to SGND.
Feedback disconnection
L6740L provides both CORE and NB sections with FB Disconnection protection. This fea-
ture acts in order to stop the device from regulating dangerous voltages in case the remote
sense connections are left floating. The protection is available for both the sections and
operates for both the positive and negative sense.
According to
●
●
To recover from a latch condition, cycle VCC or EN.
OVP
–
–
–
TH
CORE section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1-. As soon as CS1- is more than 600 mV higher than VSEN, the device latches
with all PWMx set to HiZ and ENDRVx set to zero. FLT pin is driven high. A 30 μA
pull-down current on the VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin
is driven high.
NB section (SVI only)
Positive sense is performed sourcing a 50 μA current that pulls-up the NB_VSEN pin in
order to force the device to detect an OV condition for the NB section.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin
is driven high.
=
Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
Drives the OSC/ FLT pin high.
Power supply or EN pin cycling is required to restart operations.
R
OVP
Figure
⋅
11μA
13, the protection works as follow:
=>
R
OVP
OVP
, the OVP threshold becomes the voltage present at the
=
OVP
------------------- -
11μA
TH
OVP
=11 μA current, the programmed voltage
L6740L