IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 11

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

PIN DESCRIPTIONS (CONTINUED)
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
Q[39:0]
See Pin No.
table for details)
RCLK0
(V17)
RCLK1-(V16) Read Clock 1/2/3
RCLK2-(V15)
RCLK3-(V14)
RCS0
(U13)
RCS1-(T13)
RCS2-(V12)
RCS3-(U12)
RDDR
(B7)
REN0
(U15)
REN1-(U14)
REN2-(T14)
REN3-(V13)
SCLK
(B14)
SDO
(C17)
SREN
(B15)
SWEN
(C16)
Symbol &
Pin No.
Data Output Bus
Read Clock 0
Read Chip Select 0 HSTL-LVTTL If Mux mode is selected this is the read chip select input for the read port. All read operations will occur
Read Chip Select
1/2/3
Read Port DDR
Read Enable 0
Read Enable 1/2/3
Serial Clock
Serial Data Output
Serial Read Enable HSTL-LVTTL When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF
Serial Write Enable
Name
HSTL-LVTTL These are the data outputs for the device. Data is read from the part using the respective read
HSTL-LVTTL If Mux mode is selected this is the clock input for the read port. All read port operations will be
HSTL-LVTTL If Mux mode is selected these clock inputs are ignored and if unused can be tied to GND.
HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
HSTL-LVTTL If Mux mode is selected this is the read enable input for the read port. All read operations will occur
HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
HSTL-LVTTL Serial clock for writing and reading the PAE and PAF offset registers. On the rising edge of each
HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded
OUTPUT
OUTPUT
I/O TYPE
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
(1)
(2)
(2)
If Demux or Broadcast mode is selected these are the read clock inputs for Queues 1, 2, and 3
offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising
port clock(s) and enable(s). If Mux mode is selected this is a single data output bus providing Bus-
Matching of x10, x20 or x40 bits. If Demux or Broadcast mode is selected these outputs become four
separate busses from the four separate Queues. Q[9:0] is Queue[0], Q[19:10] is Queue[1], Q[29:20]
is Queue[2], Q[39:30] is Queue[3]. Any unused outputs should be left floating. Note, that the outputs
are NOT 3.3V tolerant.
synchronous to this clock input.
If Demux or Broadcast mode is selected this is the read clock input for Queue 0. All read port operations
on Queue 0 will be synchronous to this clock input.
respectively. All read port operations on Queue 1, Queue 2 and Queue 3 will be synchronous to clock
inputs RCLK1, RCLK2 and RCLK3 respectively.
synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected this is the read chip select input for Queue 0. All read operations
on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected these are the read chip select inputs for Queues 1, 2 and
3 respectively. All read operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the
RCLK1, 2 and 3 input respectively, provided that the corresponding read enable and read chip
select inputs are LOW.
During master reset, this pin selects the output port to operate in DDR or SDR format. If RDDR is HIGH,
then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR
is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.
synchronous to the RCLK0 clock input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected this is the read enable input for Queue 0. All read operations
on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected these are the read enable inputs for Queues 1, 2 and 3
respectively. All read operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the
RCLK0, 1, 2 and 3 inputs respectively, provided that the corresponding read enable and read chip
select inputs are LOW.
SCLK, when SWEN is LOW, one bit of data is shifted from the FWFT/SI pin into the PAE and PAF offset
registers. On the rising edge of each SCLK, when SREN is LOW, one bit of data is shifted out of the
PAE and PAF offset registers. The reading of the PAE and PAF offset registers are non-destructive.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied to V
This output is used to read data from the programmable flag offset registers. It is used in conjunction
with the SREN and SCLK signals.
edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied to V
into the PAE and PAF registers. If programming of the PAE/PAF offset registers is done via the
JTAG port, this input must be tied to V
PAE and PAF registers, so the value of the registers is changed on each clock
11
Description
CC
. On each clock, data is shifted into and through the actual
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009
CC
CC
.
.