IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 24

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

HSTL/LVTTL I/O
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL V
driven to 0.75V or 0.9V respectively. Typically a logic HIGH in HSTL would
be V
is LOW during master reset, then all applicable LVTTL or HSTL signals will be
configured for LVTTL operating voltage levels. In this configuration V
be set to the static core voltage of 2.5V. Table 5 illustrates which pins are and
are not associated with this feature. Note that all “Static Pins” must be tied to V
or GND. These pins are CMOS only and are purely device configuration pins.
Note the IOSEL pin should be tied HIGH or LOW and cannot toggle before and
after master reset.
BUS MATCHING
output bus can be either 10 bits, 20 bits or 40 bits wide, depending on which
operating mode the device is configured to. The bus width of both the input and
output port is determined during master reset using the input and output width
setup pins (IW[1:0], OW[1:0]). The selected port width is applied to all four Queue
ports, such that all four Queues will be configured for either x10, x20 or x40 bus
TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The inputs and outputs of this device can be configured for either LVTTL or
The write and read port has bus-matching capability such that the input and
D[39:0]
WCLK0/1/2/3
WEN0/1/2/3
FF0/1/2/3
WCS0/1/2/3
CFF/CIR
PAF0/1/2/3
REF
Write Port
±300mV and a logic LOW would be V
CEF/COR
EF0/1/2/3
OR0/1/2/3
ERCLK0/1/2/3
OE0/1/2/3
PAE0/1/2/3
Q[39:0]
RCLK0/1/2/3
RCS0/1/2/3
REN0/1/2/3
EREN[3:0]
Read Port
REF
±300mV. If the IOSEL pin
LVTTL/HSTL/eHSTL
TCK
TRST
TMS
TDI
TDO
JTAG
REF
REF
must be
must
CC
24
OS[1:0]
widths. When writing or reading data from a Queue the number of memory
locations available to be written or read will depend on the bus width selected
and the density of the device.
of 32,768 x 10 for the IDT72T55248, 65,536 x 10 for the IDT72T55258, or
131,072 x 10 for the IDT72T55268. If the write/read port is 20 bits wide, this
provides the user with a Queue depth of 16,384 x 20 for the IDT72T55248,
32,768 x 20 for the IDT72T55258, or 65,536 x 20 for the IDT72T55268. If the
write/read port is 40 bits wide, this provides the user with a Queue depth of 8,192
x 40 for the IDT72T55248, 16,384 x 40 for the IDT72T55258, or 32,768 x 40
for the IDT72T55268. The Queue depths will always have a fixed density of
327,680 bits for the IDT72T55248, 655,360 bits for the IDT72T55258 and
1,310,072 bits for the IDT72T55268 regardless of bus-width configuration on
the write/read port.
as in single data rate since one word written or read on both the rising and falling
edge of clock. Therefore in DDR, the Queue depths will be half of what it is
mentioned above. For instance, if the write/read port is 10 bits wide, the depth
of each Queue is 16,384 x 10 for the IDT72T55248, 32,768 x 10 for the
IDT72T55258, or 65,536 x 10 for the IDT72T55268.
FSEL[1:0]
IS[1:0]
PD
MRS
PRS0/1/2/3
FWFT/SI
Control Pins
If the write/read port is 10 bits wide, this provides the user with a Queue depth
When the device is operating in double data rate, the word is twice as large
See Figure 5, Bus-Matching Byte Arrangement for more information.
SCLK
SREN
SWEN
FWFT/SI
SDO
Serial Port
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
STATIC CMOS SIGNALS
IOSEL
IW[1:0]
MD[1:0]
OW[1:0]
PFM
RDDR
WDDR
FEBRUARY 01, 2009
Static Pins