IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 9

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IDT72T55268L5BB

Manufacturer Part Number
IDT72T55268L5BB
Description
IC CTRL QUADMUX FLOW 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72T55268L5BB

Configuration
Dual
Density
4.5Mb
Access Time (max)
3.6ns
Word Size
36b
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
200MHz
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Supply Current
150mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T55268L5BB
PIN DESCRIPTIONS
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
CEF/COR
(U6)
CFF/CIR
(T6)
D[39:0]
(See Pin No.
table for details)
EF0/1/2/3/-
OR0/1/2/3
(See Pin No.
table for details)
ERCLK0
(R18)
ERCLK1/2/3
(ERCLK1-T18 1/2/3
ERCLK2-U18
ERCLK3-V18)
EREN0
(J17)
EREN1/2/3
(EREN1-J16
EREN2-K16
EREN3-K17)
FF0/1/2/3-
IR0/1/2/3
(See Pin table) 0/1/2/3
FSEL [1:0]
(FSEL1-C5
FSEL0-B6)
FWFT/SI
(B16)
IOSEL
(D5)
IS[1:0]
(IS1-V1
IS0-V2)
Symbol &
Pin No.
Composite Empty/
Composite Output
Ready Flag
Composite Full/
Composite Input
Data Input Bus
Empty Flags 0/1/2/3 HSTL-LVTTL This is the Empty Flag (Standard IDT mode) or Output Ready Flag (FWFT mode) corresponding
Flags 0/1/2/3
Echo Read Enable 0 HSTL-LVTTL If Mux mode is selected this is the echo read enable output for the read port.
1/2/3
Full Flags 0/1/2/3 or HSTL-LVTTL This is the Full Flag (Standard IDT mode) or Input Ready Flag (FWFT mode) corresponding to
Flag Select
First Word Fall
Through/ Serial
Input
I/O Select
Input Select
or Output Ready
Echo Read Clock 0 HSTL-LVTTL If Mux mode is selected this is the only echo clock output available for the read port.
Echo Read Clock
Echo Read Enable
Input Ready Flags
Ready flag
Name
HSTL-LVTTL If Mux mode is selected this flag will represent the exact status of the current Queue being read
HSTL-LVTTL If Mux mode is selected this output is not used and can be left floating.
HSTL-LVTTL These are the data inputs for the device. Data is written into the part using the respective write port
HSTL-LVTTL If Mux mode is selected these clock outputs are inactive and can be left floating.
HSTL-LVTTL If Mux mode is selected these outputs are inactive and can be left floating.
HSTL-LVTTL During master reset, the FSEL pins are used to select one of four default PAE and PAF offsets.
HSTL-LVTTL During master reset, FWFT is HIGH then the First Word Fall Through mode is selected. If FWFT
HSTL-LVTTL If Mux or Broadcast mode is selected these inputs are not used and should be tied to GND.
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
without the user having to observe the empty flag corresponding to the current Queue.
If Demux or Broadcast mode is selected this output is not used and can be left floating.
If Demux mode is selected this flag will represent the exact status of the current Queue being written
without the user having to observe the full flag corresponding to the current Queue.
If Broadcast mode is selected this flag goes active when any one of the four Queues goes full and
inactive when all four Queues are not full.
clock(s) and enable(s). If Demux or Broadcast mode is selected this is a single data input bus providing
Bus-Matching of x10, x20 or x40 bits. If Mux mode is selected these inputs become four separate
busses to the four separate Queues. D[9:0] is Queue[0], D[19:10] is Queue[1], D[29:20] is Queue[2],
D[39:30] is Queue[3]. Any unused inputs should be tied to GND. Note the inputs are 3.3V tolerant
in LVTTL mode.
to each of the four Queues on the read port. EF indicates whether or not the Queue is empty.
OR indicates whether or not there is valid data available at the outputs. These flags always represent
the status of the corresponding Queue at all times in every mode.
If Demux or Broadcast mode is selected this is the echo read clock output for Queue 0.
Echo read clock always follows RCLK0 with an associated delay.
If Demux or Broadcast mode is selected these are the echo read clock outputs for Queues 1, 2, and
3 respectively.
ERCLK1, ERCLK2 and ERCLK3 always follow RCLK1, RCLK2 and RCLK3 respectively.
If Demux or Broadcast mode is selected this is the echo read enable input for Queue 0.
Echo Read Enable is synchronous to the RCLK input and is active when a read operation has occurred
and a new word has been placed onto the data output bus.
If Demux or Broadcast mode is selected these are the echo read enable outputs for Queues 1, 2 and
3 respectively.
Echo Read Enable is synchronous to the RCLK input and is active when a read operation has occurred
and a new word has been placed onto the data output bus.
each of the four Queues on the write port. FF indicates whether or not the Queue is full.
IR indicates whether or not there is valid space for writing data onto the Queue.
All four internal Queues are programmed to the same PAE/PAF offset value. Values are: 00 = 7;
01 = 63; 10 = 127; 11 = 1023
is LOW the IDT Standard mode is selected. After master reset this pin is used for the serial data
input for the programming of the PAE and PAF flags offset registers.
This input determines whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL
pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be
set to HSTL. If IOSEL is LOW then LVTTL is selected. This signal must be tied to either V
GND for proper operation.
If Demux mode is selected these inputs select one of the four Queues to be written into on the write
port. The address on the input select pins is setup with respect to the rising edge of WCLK0.
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009
CC
or

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