IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 64

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

D[39:0]
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
Q[39:0]
WCLK
ERCLK
RCLK
WEN
REN
EREN
PD
All input and output signals will also resume after this time period.
W
D1
t
DS
W
D10
t
t
A
ERCLK
W
t
DH
D2
t
DS
t
W
A
D11
W
D3
t
DH
t
A
W
(1)
D4
1
t
EREN
Figure 39. Power Down Operation
2
64
3
4
Hi-Z
t
PDHZ
(7)
Hi-Z
t
PDL
COMMERCIAL AND INDUSTRIAL
Hi-Z
t
PDLZ
t
PDH
TEMPERATURE RANGES
1µs
(2)
(2)
FEBRUARY 01, 2009
t
W
PDH
W
t
DS
DH
D12
(2)
(8)
t
DH
t
DS
W
t
A
6157 drw36
t
D13
EREN
W
DS