IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 31

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

HIGH-to-LOW in DDR) transition of the write clock(s). It is permissible to stop
the write clock(s). Note that while the write clocks are idle, the FF/IR0/1/2/3 and
PAF0/1/2/3 flags will not be updated unless it is operating in asynchronous
timing mode (PFM=00). The write clocks can either be independent or
coincident of one another.
All other write clocks inputs should be tied to GND.
WRITE ENABLE (WEN0/1/2/3)
depending on the mode selected, one for each individual Queues in memory.
When the write enable input is LOW on the rising edge of WCLK in single data
rate, data is loaded on the rising edge of every WCLK cycle, provided the
device is not full and the write chip select (WCS) is enabled. The setup and
hold times are referenced with respect to the rising edge of WCLK only. When
the write enable input is LOW on the rising edge of WCLK in double data rate,
data is loaded into the selected Queue on the rising and falling edge of every
WCLK cycle, provided the device is not full and the write chip select (WCS)
is enabled. In this mode, the data setup and hold times are referenced with
respect to the rising and falling edge of WCLK. Note that WEN and WCS are
sampled only on the rising edge of WCLK in either data rate modes.
read operation. When the write enable(s) and write chip select(s) are HIGH,
no new data is written into the corresponding Queue on each WCLK cycle. The
four write enables operate independent of one another.
write enables should be tied to V
WRITE CHIP SELECT (WCS0/1/2/3)
depending on the mode selected, one for each individual Queues in memory.
The write chip selects disables all Write Port inputs for each individual Queue
if it is held HIGH. To perform normal write operations for each individual Queue,
the write chip select must be enabled, held LOW. The four write chip selects
are completely independent of one another.
rate, data is loaded on the rising edge of every WCLK cycle, provided the
device is not full and the write enable (WEN) of the corresponding Queue is
LOW. When the write chip select is LOW on the rising edge of WCLK in double
data rate, data is loaded into the selected Queue on the rising and falling edge
of every WCLK cycle, provided the device is not full and the write enable (WEN)
of the corresponding Queue is LOW.
rate, the write port is disabled and no words are written on the rising edge of
WCLK into the Queue, even if WEN is LOW. If the write chip select is HIGH on
the rising edge of WCLK in double data rate, the write port is also disabled and
no words are written on the rising and falling edge of WCLK into the Queue,
even if WEN is LOW. Note that WCS is sampled on the rising edge of WCLK
only in either data rate modes.
write chip selects should be tied to V
WRITE DOUBLE DATA RATE (WDDR)
the write port will be set to double data rate mode. In this mode, all write
operations are based on the rising and falling edge of the write clocks, provided
that write enables and write chip selects are LOW for the rising clock edges.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
Data setup and hold times must be met with respect to the LOW-to-HIGH (and
In Demux and Broadcast Write mode, only the WCLK0 input is available.
There are a possible total of four write enables available in this device
Data is stored in the Queues sequentially and independently of any ongoing
In Demux and Broadcast mode, only the WEN0 input is available. All other
There are a possible total of four write chip selects available in this device
When the write chip select is LOW on the rising edge of WCLK in single data
When the write chip select is HIGH on the rising edge of WCLK in single data
In Demux and Broadcast mode, only the WCS0 input is available. All other
When the write double data rate (WDDR) pin is HIGH prior to master reset,
CC
.
CC
.
31
In double data rate the write enable signals are sampled with respect to the rising
edge of write clock only, and a word will be written on both the rising and falling
edge of write clock regardless of whether or not the write enables are active
on the falling edge of write clock.
this mode, all write operations are based on only the rising edge of the write
clocks, provided that write enables and write chip selects are LOW during the
rising edge of write clock. This pin should be tied HIGH or LOW and cannot
toggle before or after master reset.
READ CLOCK (RCLK0/1/2/3)
depending on the mode selected, each corresponding to the individual Queues
in memory. A read cycle is initiated on the rising and/or falling edge of the RCLK
input. If the read double data rate (RDDR) mode pin is tied HIGH, data will be
read on both the rising and falling edge of RCLK0/1/2/3, provided that REN0/
1/2/3 and RCS0/1/2/3 are enabled. If RDDR is tied LOW, data will be read
only on the rising edge of RCLK0/1/2/3 provided that REN0/1/2/3 and RCS0/
1/2/3 are enabled. The four read clocks are completely independent of one
another.
the Queues. It is permissible to stop the read clocks. Note that while the read
clocks are idle, the EF/OR0/1/2/3 and PAE0/1/2/3 flags will not be updated
unless it is operating in asynchronous timing mode (PFM=0). The write and
read clocks can either be independent or coincident.
should be tied to GND.
READ ENABLE (REN0/1/2/3)
depending on the mode selected, one for each individual Queue in memory.
When the read enable input is LOW on the rising edge of RCLK in single data
rate, data will be read on the rising edge of every RCLK cycle, provided the
device is not empty and the read chip select (RCS) is enabled. The associated
data access time (tA) is referenced with respect to the rising edge of RCLK.
When the read enable input is LOW on the rising edge of RCLK in double data
rate, will be read on the rising and falling edge of every RCLK cycle, provided
the device is not empty and RCS is enabled. In this mode, the data access times
are referenced with respect to the rising and falling edges of RCLK. Note that
REN is sampled only on the rising edge of RCLK in either data rate modes.
write operation. When the read enable(s) and read chip select(s) are HIGH,
no new data is read on each RCLK cycle. The four read enables operate
independent of one another.
empty flag of each Queue will go LOW with respect to RCLK, when the total
number of words in the Queue has been read out, thus inhibiting further read
operations. Upon the completion of a valid write cycle, the empty flag will go
HIGH with respect to RCLK two cycles later, thus allowing another read to
occur, providing t
be tied to V
READ CHIP SELECT (RCS0/1/2/3)
each corresponding to the individual Queue in memory. The read chip select
inputs provides synchronous control of the read port for each individual Queue.
When the read chip select is held LOW, the next rising edge of the correspond-
When WDDR is LOW, the write port will be set to single data rate mode. In
There are a possible total of four read clocks available in this device
There is an associated data access time (t
In Mux mode, only the RCLK0 input is available. All other read clock inputs
There are a possible total of four read enables available in this device
Data is stored in the Queues sequentially and independently of any ongoing
To prevent reading from an empty Queue in the IDT Standard mode, the
In Mux mode, only the REN0 input is available. All other read enables should
There are a possible total of four read chip selects available in this device,
CC
.
SKEW
of WCLK to RCLK is met.
COMMERCIAL AND INDUSTRIAL
A
TEMPERATURE RANGES
) for the data to be read out of
FEBRUARY 01, 2009