FAN1851AN Fairchild Semiconductor, FAN1851AN Datasheet - Page 6
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FAN1851AN
Manufacturer Part Number
FAN1851AN
Description
IC CTRLR AC GRND FAULT 8DIP
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN1851AN.pdf
(11 pages)
Specifications of FAN1851AN
Applications
*
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Product
Voltage References
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FAN1851AN
Manufacturer:
MICROCHIP
Quantity:
2
FAN1851A
Application Information
A typical ground fault interrupter circuit is shown in
Figure 10. It is designed to operate on 120 VAC line voltage
with 5mA normal fault sensitivity.
A full-wave rectifier bridge and a 15k /2W resistor are used
to supply the DC power required by the IC. A 1 µF capacitor
at the "+V
age and is also connected across the SCR to allow firing of
the SCR on either half-cycle. When a fault causes the SCR to
trigger, the circuit breaker is energized and line voltage is
removed from the load.
At this time no fault current flows and the C
rent increases from I
quickly resets both the timing capacitor and the output latch.
The circuit breaker can be reset and the line voltage again
supplied to the load, assuming the fault has been removed.
A 1000:1 sense transformer is used to detect the normal
fault. The fault current, which is basically the difference in
current between the hot and neutral lines, is stepped down by
1000 and fed into the input pin of the operational amplifier
through a 10µF capacitor. The 0.0033µF capacitor between
the "- Input" pin and the "+ Input" pin and the 200pF capaci-
tor between "+ Input" and "Ground" pins are added to obtain
better noise immunity. The normal fault sensitivity is deter-
mined by the timing capacitor discharging current, I
can be calculated by:
At the decision point, the average fault current just equals
the threshold current, I
Where I
tional amplifier and the factor of 2 is due to the fact that I
charges the timing capacitor only during one half-cycle,
while I
0.91 converts the rms value to an average value. Combining
equations (1) and (2) we have:
For example, to obtain 5mA(rms) sensitivity for the circuit
in Figure 7 we have:
6
I
I
R
R
TH
TH
SET
TH
SET
F
(rms) is the rms input fault current to the opera-
=
=
S
discharges the capacitor continuously. The factor
" pin is used to filter the ripple of the supply volt-
=
------------ -
R
I
------------------ -
=
F
7V
SET
----------------------------------- -
I
----------------------------- -
5 mA 0.91
----------------------------- -
F
rms
2
rms
1000
7V
7V
TH
2
TH
0.91
to 3I
0.91
.
=
TH
1.5M
(see Block Diagram). This
T
discharge cur-
TH
. I
TH
F
(1)
(2)
(3)
(4)
The correct value for R
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of R
on the specific sense transformer used and FAN1851A toler-
ances. Inasmuch as UL943 specifies a sensitivity “window”
of 4mA to 6mA, a provision should be made to adjust R
with a potentiometer.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capacitor, C
proper selection of C
ing design example should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GFI
start-up (S1 closure) with both a heavy normal fault and a
2 grounded neutral fault present. This situation is shown in
Figure 8.
UL943 specifies 25ms average trip time under these condi-
tions. Calculation of C
normal fault only is as follows:
1.
2.
3.
4.
Line
Start with a
turn-on time (15k and 1µF). Subtract 8ms potential
loss of one half-cycle due to fault current sense of
half-cycles only.
Subtract 4ms time required to open a sluggish circuit
breaker.
This gives a total
that could be allowed.
To generate 8ms value of integration time that accom-
modates component tolerances and other variables:
C
T
=
I
-----------
T
. Due to the large number of variables involved,
V
T
S1
Neutral
25ms specification. Subtract 3ms GFI
Hot
Figure 8. Example
T
T
is best done empirically. The follow-
SET
10ms maximum integration time
based upon charging currents due to
500
can also be determined from the
R
GFI
B
(0.8)I
PRODUCT SPECIFICATION
(0.2)I
Neutral
Hot
REV. 2.0.1 6/17/05
R
0.4
N
SET
depends
500
R
I
B
SET
(5)