MT4VDDT1664AG-40BF3 Micron Technology Inc, MT4VDDT1664AG-40BF3 Datasheet - Page 14

• Manufacturer Part Number: MT4VDDT1664AG-40BF3
• Description: MODULE DDR 128MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664AG-40BF3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 16Mx64
• Total Density: 128MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.04A
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 12: I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–21; 0°C ≤ T
pdf: 09005aef80a43556, source: 09005aef80a43534
DDA8C16_32_64x64AG.fm - Rev. D 9/04 EN
OPERATING CURRENT: One device bank; Active-Precharge;
t
Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 2;
t
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-
down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
= HIGH; Address and other control inputs changing once per clock cycle. V
V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-
down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-
Precharge;
changing twice per clock cycle; Address and other control inputs changing once
per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
(MIN); I
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with auto
precharge,
inputs change only during Active, READ, or WRITE commands
CK =
RC =
REF
for DQ, DQS, and DM
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
OUT
t
t
RC = minimum
= 0mA
RC =
t
t
CK =
CK =
DD
t
t
CK =
RAS (MAX);
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
Specifications and Conditions – 128MB
t
CK (MIN); I
PARAMETER/CONDITION
t
RC allowed;
t
CK =
OUT
t
CK (MIN); DQ, DM, and DQS inputs
= 0mA; Address and control inputs
t
CK =
t
CK (MIN); Address and control
128MB, 256MB, 512MB (x64, SR) PC3200
t
t
RC =
t
t
CK =
14
REFC =
REFC = 15.625µs
A
≤ +70°C; V
t
t
RC (MIN);
CK (MIN); CKE
t
t
CK =
CK =
t
RFC (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
t
t
CK
CK
DD
IN
= V
=
DD
SYMBOL
Q = +2.6V ±0.1V
I
I
I
I
I
I
I
DD 4 W
I
I
DD 3 N
I
DD 5 A
I
I
DD 2 P
DD 2 F
DD 3 P
DD 4 R
DD 0
DD 1
DD 5
DD 6
DD 7
MAX
1,080
1,080
1,240
1,920
2,840
-40B
920
400
200
400
24
48
32
UNITS
©2004 Micron Technology. Inc.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 41
20, 42
20, 44
24, 44
20, 43
44
45
44
20
9