MT4VDDT1664AG-40BF3 Micron Technology Inc, MT4VDDT1664AG-40BF3 Datasheet - Page 20

• Manufacturer Part Number: MT4VDDT1664AG-40BF3
• Description: MODULE DDR 128MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664AG-40BF3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 16Mx64
• Total Density: 128MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.04A
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80a43556, source: 09005aef80a43534
DDA8C16_32_64x64AG.fm - Rev. D 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
26. CK and CK# input slew rate must be ≥ 1 V/ns (≤ 2
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
-40B speed grade, slow rate must be ≥ 0.5 V/ns. If
slew rate exceeds 4 V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+300mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue
DH for each 100mv/ns reduction in slew rate. For
HP min is the lesser of
t
QH =
DD
AC level through to the target AC level, V
or V
to maintain at least the target DC level, V
or V
must not vary more than 4 percent if CKE is
t
IH
IH
HP -
(
(
AC
DC
t
).
).
QHS). The data valid window derates
t
HP (
t
t
t
CK/2),
CL minimum and
RAS (MIN) can be satis-
t
RFC [MIN]) else
t
DQSQ, and
t
DS and
128MB, 256MB, 512MB (x64, SR) PC3200
IL
IL
(
t
(
t
DC
QH
CH
AC
)
)
20
33. Normal Output Drive Curves:
34. The voltage levels used are derived from a mini-
35. V
36. V
37. This maximum value is derived from the refer-
not exceed either -200mV or 2.4V, whichever is
more positive.
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
width ≤ 3ns and the pulse width cannot be greater
than 1/3 of the cycle rate. V
(MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width cannot be greater than 1/3 of the
cycle rate.
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
(MAX) will prevail over
(MAX) condition.
t
b. The variation in driver pull-down current
d. The variation in driver pull-up current within
a. The full variation in driver pull-down current
c. The full variation in driver pull-up current
e. The full variation in the ratio of the maximum
DQSCK (MIN) +
f. The full variation in the ratio of the nominal
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
DD
184-PIN DDR SDRAM UDIMM
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
overshoot: V
and V
DD
DD
level and the referenced test load. In
Q must track each other.
t
HZ (MAX) and the last DVW.
IH
t
RPRE (MAX) condition.
(
MAX
t
LZ (MIN) will prevail over
) = V
t
DQSCK (MAX) +
DD
Q + 1.5V for a pulse
IL
undershoot: V
©2004 Micron Technology. Inc.
t
RPST
t
HZ
IL