MT4VDDT1664AG-40BF3 Micron Technology Inc, MT4VDDT1664AG-40BF3 Datasheet - Page 17

• Manufacturer Part Number: MT4VDDT1664AG-40BF3
• Description: MODULE DDR 128MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664AG-40BF3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 16Mx64
• Total Density: 128MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.04A
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12–15, 29
pdf: 09005aef80a43556, source: 09005aef80a43534
DDA8C16_32_64x64AG.fm - Rev. D 9/04 EN
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-outhigh-impedancewindowfromCK/CK#
Data-outlow-impedancewindowfromCK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with auto precharge command
ACTIVEto ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Operating Conditions
;
notes appear on pages 19–21; 0°C ≤ T
PARAMETER
AC CHARACTERISTICS
CL = 3
CL = 2.5
CL = 2
128MB, 256MB, 512MB (x64, SR) PC3200
A
17
≤ +70°C; V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
184-PIN DDR SDRAM UDIMM
t
DD
CK (2.5)
t
t
t
t
t
t
t
WPRES
t
t
t
DQSCK
t
t
t
CK (3)
CK (2)
DQSH
DQSQ
WPRE
t
SYM
DIPW
t
t
t
t
WPST
DQSL
DQSS
t
t
t
t
MRD
t
RPRE
RPST
t
WTR
t
t
t
t
t
t
DSH
t
t
QHS
RAP
RCD
RRD
t
t
t
IPW
RAS
t
t
t
DSS
t
RFC
QH
WR
DH
IH
IH
AC
CH
HP
HZ
DS
IS
IS
RC
RP
CL
LZ
= V
F
S
F
S
DD
Q = +2.6V ±0.1V
t
HP -
-0.70
-0.60
MIN
0.45
0.45
5.00
6.00
7.50
0.40
0.40
1.75
0.35
0.35
0.72
0.20
0.20
0.60
0.60
0.60
0.60
2.20
0.90
0.40
0.25
0.40
-0.7
10
40
15
55
70
15
15
10
15
0
2
t
QHS
t
CH,
-40B
t
CL
70,000
MAX
+0.70
+0.60
+0.70
13.00
13.00
0.55
0.55
7.50
0.40
1.28
0.50
1.10
0.60
0.60
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
©2004 Micron Technology. Inc.
NOTES
40, 46
40, 46
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
18, 19
31,
26
26
30
12
12
12
12
44
38
38
17
27