MT4VDDT1664AG-40BF3 Micron Technology Inc, MT4VDDT1664AG-40BF3 Datasheet - Page 21

• Manufacturer Part Number: MT4VDDT1664AG-40BF3
• Description: MODULE DDR 128MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664AG-40BF3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 16Mx64
• Total Density: 128MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.04A
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80a43556, source: 09005aef80a43534
DDA8C16_32_64x64AG.fm - Rev. D 9/04 EN
38. For slew rates greater than 1 V/ns the (LZ) transi-
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -40B modules, I
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
160
140
120
100
80
60
40
20
Figure 8: Pull-Down Characteristics
0
0.0
tion will start about 310ps earlier.
be equal to or less than V
V
even if V
42Ω of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
per DDR SDRAM device at 100 MHz.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
RFC has been satisfied.
TT
may be 1.35V maximum during power up,
DD
0.5
/V
DD
Q are 0V, provided a minimum of
1.0
DD
V
V
OUT
OUT
3N is specified to be 35mA
DD
(V)
(V)
DD
Q, V
1.5
+ 0.3V. Alternatively,
TT
, and V
2.0
Minimum
REF
128MB, 256MB, 512MB (x64, SR) PC3200
must
TT
2.5
21
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. This is the DC voltage supplied at the DRAM and
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset, fol-
lowed by 200 clock cycles before any READ com-
mand.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±100mV.
Figure 9: Pull-Up Characteristics
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
2N specifies the DQ, DQS, and DM to be
2F is “worst case.”
0.5
DD
DD
2F, I
2
F
DD
1.0
except I
V
DD
2N, and I
Q - V
OUT
(V)
1.5
DD
DD
2Q specifies the
©2004 Micron Technology. Inc.
2Q are similar,
2.0
DD
2Q is
2.5