MT16VDDT6464AG-335GB Micron Technology Inc, MT16VDDT6464AG-335GB Datasheet - Page 10

• Manufacturer Part Number: MT16VDDT6464AG-335GB
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT6464AG-335GB

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
1. For a burst length of two, A1–Ai select the two-data-
2. For a burst length of four, A2–Ai select the four-data-
3. For a burst length of eight, A3–Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9 for 256MB, 512MB;
LENGTH
BURST
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
element block; A0–A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 for 1GB, 2GB.
2
4
8
SPEED
-26A
-335
-262
-265
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
A1 A0
Burst Definition Table
CAS Latency (CL) Table
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75
75
75
75
CLOCK FREQUENCY (MHZ)
ALLOWABLE OPERATING
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
CL = 2
ORDER OF ACCESSES WITHIN
SEQUENTIAL
f
f
f
f
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
133
133
133
100
0-1
1-0
A BURST
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
75
75
75
75
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f
f
f
f
0-1
1-0
167
133
133
133
10
256MB, 512MB, 1GB, 2GB (x64, DR)
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Figure 7,
CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.
operation or incompatibility with future versions may
result.
Operating Mode
MODE REGISTER SET command with bits A7–A11
(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) each
set to zero, and bits A0–A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9–A11 (256MB), A7
and A9–A12 (512MB, 1GB), or A7 and A9–A13
(2GB)each set to zero, bit A8 set to one, and bits A0–A6
set to the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) are
reserved for future use and/or test modes. Test modes
COMMAND
COMMAND
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11
DQS
DQS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 6: CAS Latency Diagram
CK#
CK#
DQ
DQ
184-PIN DDR SDRAM UDIMM
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
©2004 Micron Technology, Inc.
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n