MT16VDDT6464AG-335GB Micron Technology Inc, MT16VDDT6464AG-335GB Datasheet - Page 9

• Manufacturer Part Number: MT16VDDT6464AG-335GB
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT6464AG-335GB

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(256MB) or A7–A12 (512MB, 1GB), or A7–A13 (2GB)
specify the operating mode.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3-
Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given config-
uration; see Note 5, of Table 6, Burst Definition Table,
on page 10). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Mode register bits A0–A2 specify the burst length,
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
The READ latency is the delay, in clock cycles,
256MB, 512MB, 1GB, 2GB (x64, DR)
9
256MB Module
* M15 and M14 (BA1 and BA0)
* M13 and M12 (BA0 and BA1) must be “0, 0” to select the
512MB and 1GB Modules
* M14 and M13 (BA0 and BA1) must be “0, 0” to select the
2GB Module
0*
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
base mode register (vs. the extended mode register).
base mode register (vs. the extended mode register).
BA1
15
Figure 5: Mode Register Definition
0*
0*
14
BA1
BA0
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
0*
13
184-PIN DDR SDRAM UDIMM
BA1
13
BA0
A13
13
0*
12
12
BA0
A12 A11
12
A12 A11
Operating Mode
Operating Mode
11
A11
11
11
M13
Operating Mode
0
0
-
10
10
A10
10
A10
A10
M12 M11
0
0
-
9
9
A9
9
A9
A9
0
0
-
8
A8
8
A8
8
A8
M10
0
0
-
Diagram
7
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
CAS Latency BT
M6
CAS Latency BT
0
0
CAS Latency BT
-
0
0
0
0
1
1
1
1
6
6
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
5
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
4
4
M6-M0
M3
0
1
Valid
Valid
3
3
3
-
Burst Length
Burst Length
Burst Length
M2
2
2
0
0
0
0
1
1
1
1
2
A2 A1 A0
A2 A1 A0
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
©2004 Micron Technology, Inc.
0
1
0
1
0
1
0
1
0
0
0
Interleaved
Burst Type
Sequential
Burst Length
Mode Register (Mx)
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
Address Bus
2
4
8