PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 279

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

REGISTER 23-2:
© 2009 Microchip Technology Inc.
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-1
bit 0
bit 4-0
Note 1:
2:
To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module in
Disable mode before putting device to Sleep.
If buffer is configured as receiver, EICODE bits will contain ‘10000’ upon interrupt.
OPMODE2
OPMODE2
bit 7
OPMODE2:OPMODE0: Operation Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
Mode 0:
Unimplemented: Read as ‘0’
ICODE3:ICODE1: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code
indicates the source of the interrupt. By copying ICODE3:ICODE1 to WIN2:WIN0 (Mode 0) or
EICODE4:EICODE0 to EWIN4:EWIN0 (Mode 1 and 2), it is possible to select the correct buffer to map into
the Access Bank area. See Example 23-2 for a code example. To simplify the description, the following
table lists all five bits.
Unimplemented: Read as ‘0’
Mode 1, 2:
EICODE4:EICODE0: Interrupt Code bits
See ICODE3:ICODE1 above.
No interrupt
Error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
RXB0 interrupt
RXB1 interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B5 interrupt
R-1
R-1
CANSTAT: CAN STATUS REGISTER
(1)
(1)
OPMODE1
OPMODE1
R-0
R-0
(1)
(1)
OPMODE0
OPMODE0
W = Writable bit
‘1’ = Bit is set
Mode 0
00000
00010
00100
00110
01000
01010
01100
00010
-----
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-----
-----
-----
-----
-----
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PIC18F2682/2685/4682/4685
R-0
R-0
(1)
(1)
EICODE4 EICODE3
R-0
R-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Mode 1
00000
00010
00100
00110
01000
10001
10000
01110
10000
10001
10010
10011
10100
10101
10110
10111
ICODE3
R-0
R-0
EICODE2
ICODE2
R-0
R-0
00000
00010
00100
00110
01000
-----
10000
01110
10000
10000
10010
10011
10100
10101
10110
10111
Mode 2
x = Bit is unknown
EICODE1
ICODE1
R-0
R-0
(2)
(2)
(2)
(2)
(2)
DS39761C-page 279
EICODE0
U-0
R-0
—
bit 0