DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 132
![KIT REF DESIGN DTMF DECODER](/photos/9/6/90685/dtmfdecoder-rd_sml.jpg)
DTMFDECODER-RD
Manufacturer Part Number
DTMFDECODER-RD
Description
KIT REF DESIGN DTMF DECODER
Manufacturer
Silicon Laboratories Inc
Specifications of DTMFDECODER-RD
Mfg Application Notes
DTMF Decoder Ref Design AppNote
Main Purpose
Telecom, DTMF Decoder
Embedded
No
Utilized Ic / Part
C8051F300
Primary Attributes
8kHz Sampling Rate ADC
Secondary Attributes
16 Goertzel Filters
Processor To Be Evaluated
C8051F300
Interface Type
RS-232
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
336-1283
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C8051F300/1/2/3/4/5
14.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 14.2), which is not user
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see
ter/Timer with Auto-Reload” on page
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of five
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8. For any
given Timer 1 clock source, the UART0 baud rate is determined by Equation 14.1.
Where T1
value). Timer 1 clock frequency is selected as described in
reference for typical baud rates and system clock frequencies is given in Tables 14.1 through 14.6. Note
that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1
(see
132
Section “15.1. Timer 0 and Timer 1” on page 143
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
Figure 14.2. UART0 Baud Rate Logic
RX Timer
Equation 14.1. UART0 Baud Rate
UartBaudRate
Timer 1
TH1
TL1
145). The Timer 1 reload value should be set so that overflows will
Overflow
Overflow
Rev. 2.9
=
------------------------------ -
256 T1H
for more details).
T1
Section “15.2. Timer 2” on page
–
CLK
2
2
Section “15.1.3. Mode 2: 8-bit Coun-
UART0
1
-- -
2
RX Clock
TX Clock
151. A quick
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