DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 97

• Manufacturer Part Number: DTMFDECODER-RD
• Description: KIT REF DESIGN DTMF DECODER
• Manufacturer: Silicon Laboratories Inc

Specifications of DTMFDECODER-RD

• Mfg Application Notes: DTMF Decoder Ref Design AppNote
• Main Purpose: Telecom, DTMF Decoder
• Embedded: No
• Utilized Ic / Part: C8051F300
• Primary Attributes: 8kHz Sampling Rate ADC
• Secondary Attributes: 16 Goertzel Filters
• Processor To Be Evaluated: C8051F300
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1283

11. Oscillators
C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive
circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL reg-
isters, as shown in Figure 11.1. The system clock can be sourced by the external oscillator circuit, the
internal oscillator, or a scaled version of the internal oscillator. The internal oscillator's electrical specifica-
tions are given in Table 11.1 on page 99.
11.1. Programmable Internal Oscillator
All C8051F300/1/2/3/4/5 devices include a programmable internal oscillator that defaults as the system
clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as
defined by SFR Definition 11.1. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a
24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may
vary ±20% from device-to-device.
Electrical specifications for the precision internal oscillator are given in Table 11.1 on page 99. The pro-
grammed internal oscillator frequency must not exceed 25 MHz. Note that the system clock may be
derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg-
ister OSCICN. The divide value defaults to 8 following a reset.
VDD
Option 2
Option 3
XTAL2
XTAL2
Option 1
Option 4
XTAL2
10M
Figure 11.1. Oscillator Diagram
XTAL1
XTAL2
OSCICL
Rev. 2.9
Circuit
Input
Programmable
Internal Clock
Generator
OSCXCN
EN
OSC
OSCICN
C8051F300/1/2/3/4/5
n
SYSCLK
97