STEVAL-IPE008V1 STMicroelectronics, STEVAL-IPE008V1 Datasheet - Page 20

• Manufacturer Part Number: STEVAL-IPE008V1
• Description: BOARD EVAL STPM01/STR715FR0
• Manufacturer: STMicroelectronics
• Type: Other Power Managementr

Specifications of STEVAL-IPE008V1

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, ARM7
• Utilized Ic / Part: STPM01, STR715FR0
• Primary Attributes: 3-Ph Energy Meter (or Single Phase)
• Secondary Attributes: Measures Active, Reactive, Apparent Power
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STPM01, STR715FR0
• Other names: 497-6412; STEVAL-IPE008V1

Theory of operation
Figure 15. ZCR signal
8.5
20/60
Period and line voltage measurement
The period module measures the period of the base frequency of the voltage channel and
checks if the voltage signal frequency is within the f
LIN signal is produced, which is low when the line voltage is rising, and high when the line
voltage is falling. This means that the LIN signal is the sign of dv/dt. With further elaboration,
the ZCR signal is also produced. On the trailing edge of LIN (line frequency) the period
counter starts counting up pulses of the f
on the status bit register (see
If the counted number of pulses between two trailing edges of LIN is higher than 2
the counting is never stopped (no LIN trailing edge) this means that the base frequency is
lower than f
If the number of pulses counted between two trailing edges of LIN is lower than 2
base frequency exceeds the limit (means it is higher than f
must be repeated three consecutive times in order to set the BFR error flag.
For example, with a 4.194304 MHz oscillator frequency and MDIV bit clear (or 8.192 MHz
with MDIV set), f
pulses between two LIN trailing edges are 34952, more than 2
low frequency limit is then:
f
With the same clock frequency, if the line frequency is 130Hz, the f
LIN trailing edges are 8066, more than 2
f
When the line frequency re-enters the nominal band, the BFR flag is automatically reset.
This BFR error flag is also assembled as part of the 8-bit status register (see
CLK
CLK
/2
/2
17
15
= 4194304/32768 = 128 Hz.
= 4194304/131072 = 32 Hz.
CLK
/2
CLK
17
Hz and a BFR (base frequency range) error flag is set.
/4 is 1048.576 MHz. If the line frequency is 30 Hz, the counted f
Table
Doc ID 10853 Rev 7
15).
13
CLK
(8192). The BFR high frequency limit is then:
/4 reference signal. The LIN signal is available
CLK
/2
17
CLK
to f
/2
15
CLK
15
(32768 pulses). The BFR
CLK
. In this case, the error
/2
15
/4 pulses between two
band. To do this, the
Table
13
15
STPM01
, the
15).
CLK
, or if
/4